The procedure below is using the
schematic-based design with the circuit "moj_schemat.sch". For HDL-based
designs, the procedure is identical..
Switch ISE system into
implementation mode:
Add new User Constraint File UCF: to the design, selecting
Implementation Constraints File:
Edit new UCF and add the FPGA
pin constraints, appropriate for your design:
It is advised to copy and
paste the UCF content from the WWW site of the corresponding laboratory exercise.
Please, change only the names of the ports in UCF, so they would be identical
as in your design.
Execute synthesis,
implementation and generation of bit file with single command Generate
Programming File: