Creating new design

Start Xilinx ISE 10.1. Select File/New Project. In window New Project Wizard enter project name.

Set Top-level source type:

- for the schematic based design entry, select Schematic,

- for the VHDL or Verilog based design entry, select HDL:

Make sure, that the folder with the files (Project location) starts with C:\Designs\.


Check the settings of the FPGA circuit and set the preferred HDL language: VHDL lub Verilog:


Do not enter anything in Create New Source window (you will add the files after creating the project), just select Next:


In the next window, also select Next:


Finally, select Finish: