Lab Home page
|Department of Microelectronic Systems, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology||
Task: Design a circuit dividing the
input clock by N.
- Provide duty cycle of the output signal as close as possible to 50% (for even N duty cycle should be exactly 50%, for odd N duty cycle should be 50% with accuracy of 1 input clock cycle).
- Enable easy change of N (e.g. by constant or generic).
- The divider must have asynchronous reset.
- Create separate testbench module, which generates all the signals necessary to test the divider. Testbench is not synthesisable.
- Before implementation, run the simulation using testbench. In simulation only, decrease N to speed up the simulation.
- To check the divider, divide 50MHz clock to obtain blinking LED LD7 with frequency of 1Hz.
- Implement the design.