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Department of Microelectronic Systems, Faculty of Electronics,
Telecommunications and Informatics, Gdansk University of Technology
Generating and using ROM
Run Xilinx ISE 8.1i Core Generator to
generate ROM to be used in the exercise.
Core Generator can be found in Windows Start Menu:
Start/Programy/Xilinx ISEXXX/Accessories/Core Generator.
Then follow the instructions:
- In the window on right side, click Create new project and point
to the directory, where generated block will be written.
- Dialog window will open, where module parameters must be written, as shown
in figure below.
- Then, after clicking on "+", unfold Menu as shown below and double click
on Single Port Block Memory 6.2.
- A new window will show up, where in 4 consecutive steps a proper parameters
must be entered (as shown on the pictures below), and finally press
- After pressing Generate, files will be written in directory
entered in paragraph a.
- In paragraph d., on the last screen, a file
"vga_bmp.coe" should be entered.
This is the file "vga_bmp.bmp" converted to the format
required by Core Generator.
- Copy the files *.edn, *.vhd, *.mif
from directory chosen in a. to project's "/src" directory.
In file *.vho there are examples of inserting the generated block
as component in VHDL.
Files *.vhd and *.mif are for simulation only.
File *.edn contains schematic diagram needed in implementation.
- In Active HDL add the files listed in paragraph g. to your design
(Menu Design / Add Files to Design...). Additionally,
files *.vhd generated by Core Generator should be excluded from synthesis
(in Synthesis Options).
- Generated ROM memory is synchronous. To read from memory, the required address
(addr) and enable = 1 (en) should be set,
then after rising edge of the clock (clk),
the content of the cell at the given address will be
presented on the output dout.