Questions for the test of Programmable Systems Engineering:

 

  1. Name three categories of digital programmable circuits (in terms of the architecture) and briefly characterize each of them.
  2. What category of digital programmable circuits deals with: coarse grade, medium grade and fine grade? Briefly characterize the above mentioned types of circuits.
  3. What kind of configuration memory is dominant in CPLDs and what is in FPGAs?
  4. Enumerate the configuration memory types with their advantages and disadvantages.
  5. In the Spartan3E FPGA, some logic functions can be implemented in one LUT cell. Specify how many input variables can have any logical function implemented in one LUT, how many input variables can have any logical function implemented in one slice, and specify the maximum number of inputs that some logic functions implemented on a single slice can have?
  6. Specify configurable parameters of the Spartan3E I/O terminals.
  7. Specify the Spartan3E configuration modes.
  8. Describe the properties and applications of the ‘week-keeper’ module in the Spartan3E.
  9. Explain the concept of ‘local routing’.
  10. Explain the concept of ‘general purpose routing’.
  11. Explain the concept of ‘global routing’.
  12. Explain the concept of ‘dedicated routing’.
  13. Explain the concept of ‘clock skew’ and provide ways to reduce or compensate it.
  14. Explain the concept of ‘Delay Locked Loop’, draw a diagram of such a loop and describe the applications.
  15. What signals can be generated by the DCM module in the Spartan3E. What are the requirements for clock signals?
  16. Name and characterize the Spartan3E single-port Block-RAM memory write modes.
  17. Enumerate the possible applications of a single-port Block-RAM memory in Spartan3E.
  18. Specify the properties and applications of a two-port Block-RAM memory in Spartan3E.
  19. Specify the functions that the LUT block in the Spartan3E CLB cell can implement.
  20. Specify differences of the architecture between PLA and PAL circuits.
  21. Enumerate and briefly describe the levels of abstraction used in the hardware description.
  22. Enumerate the methods of digital circuit description.
  23. What is a synthesizable subset of VHDL? Provide an example of a non-synthesizable statement.
  24. What is the resolution function?
  25. Provide ways to avoid forbidden states in state machines.
  26. What is the metastability of flip-flops?
  27. Name and briefly describe three methods of synthesis using functional blocks in FPGAs.
  28. Specify the properties of the variables in the processes.
  29. Specify the properties of the variables in the functions.
  30. Discuss the essential differences between variables and signals.
  31. Discuss the ways of parameterization of the design modules.
  32. What is the ‘unconstrained vector’? Describe the applications.
  33. What are delta cycles? Give an example.
  34. What should be the number of iterations of the synthesizable loop?
  35. What is the ‘generate’ statement for?

  36. Write a synchronous process in VHDL that implements a synthesizable n-bit multiplier (on unsigned binary numbers). Do not use the * operator. The process should start the multiplication when the mul_start signal (std_logic type) is triggered. During the multiplication the mul_busy signal (std_logic type) should be asserted. The multiplier inputs should be given to the signals mul_in_1 and mul_in_2 (these are std_logic_vector signals), and the result should be given to the mul_result register (2n bit - also std_logic_vector). Provide definitions of the signals used.

    multiplier: process (clk, rst)
    .....
    end process;

  37. Write a synchronous process in VHDL that implements the synthesizable n-bit Johnson's counter. Please operate on signals of type std_logic and std_logic_vector. Provide definitions of the signals used. Secure the counter against locking in prohibited state (or states).

    johnson: process (clk, rst)
    .....
    end process;

  38. Write a synchronous process in VHDL that implements a synthesizable state machine that controls the operation of the wiper motor. The machine has input signals: wipe_on (means wiper on), home_pos (wiper rest position), end_pos (wiper end position). The state machine generates the output signals: motor_on (switches on the wiper motor), motor_rev (switches the direction of rotation to reverse). Remember to synchronize input signals from sensors (using D flip-flops). Provide definitions of the signals used.

    wiper: process (clk, rst)
    .....
    end process;