Task:
Design a
four-bit Johnson counter.
Inputs:
- button BTNC on the prototype board (central button) (in remote mode – virtual button BTN0) representing
the clock (signal name - clk_i),
- button BTNR on the prototype board (right button) (in remote mode – virtual button BTN3) representing
the asynchronous reset (signal name - rst_i ).
Outputs:
- LED LD0 - bit 0 of the Johnson counter ( signal name - led_o(0) ),
- LED LD1 - bit 1 of the Johnson counter ( signal name - led_o(1) ),
- LED LD2 - bit 2 of the Johnson counter ( signal name - led_o(2) ),
- LED LD3 - bit 3 of the Johnson counter ( signal name - led_o(3) ).
In
stationary mode, the clock is generated by pressing a mechanical button and
therefore contact vibrations may occur, i.e. generation of more than one clock
pulse after a single push of the button. In
remote mode, the virtual buttons have a contact vibration emulation mode that
must be disabled.
Perform a functional simulation and verify the circuit practically by programming
a prototype FPGA board.
Minimum requirements for simulation and verification on the board: perform a reset twice - at the beginning of the simulation/verification and during it, but in such a way that its operation is visible at the counter’s output. The simulation/verification must cover all counter’s states. Any clock frequency can be used for the simulation.
Part of the main (top level) VHDL design file with signal declaration:
entity top is
Port ( clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_o : out STD_LOGIC_VECTOR (3 downto 0));
end top;
Design
constraints file for Nexys-A7 board (FPGA chip xc7a100tcsg324-1): iup4s.xdc
Design constraints file for remote mode (with support for virtual buttons): iup4z.xdc
The following Vivado warnings can be ignored for this exercise:
[Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
[Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
[Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer.
[Place 30-574] Poor placement for routing between an IO pin and BUFG.