Task: Design a frequency divider by N. Make the duty cycle of the output waveform as close as possible to 1/2 (for even N it should be exactly 1/2). It should also be possible to change the value of N easily (e.g. using a constant or generic definition). The divider should have an asynchronous reset input that will reset the counter in the divider (the output after reset should be zero).
Inputs:
- 100 MHz clock signal ( signal name - clk_i ),
- button BTNR on the prototype board (right button) (in remote mode – virtual button BTN3) representing
the asynchronous reset (signal name - rst_i ).
Outputs:
- LED LD0 – divided clock ( signal name - led_o ).
Perform a functional simulation and verify the circuit practically by programming a prototype FPGA board.
Minimum requirements for simulation and verification on the board: perform a reset twice - at the beginning of the simulation/verification and during it, but in such a way that its operation is visible at the counter’s output. The simulation / verification must show several LED flashing cycles.
For the simulation purposes, set the divisor N to a number equal to the sum of the digits of the index of the student completing the exercise (in the case of a group - take the index number of any student in the group) and simultaneously visualize on the same graph both the clock signal and the divider's output. Clock frequency in the simulation - 100 MHz.
To verify on the board, set the divisor N so as to obtain LED LD0 flashing with a frequency of 1Hz.
Part of the main (top level) VHDL design file with signal declaration:
entity top is
Port ( clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_o : out STD_LOGIC);
end top;
Design
constraints file for Nexys-A7 board (FPGA chip xc7a100tcsg324-1): iup5s.xdc
Design constraints file for remote mode (with support for virtual buttons): iup5z.xdc