RS-232 port monitor

Exercise:

Design data monitor for RS232 port running with following line parameters: 9600bps, 8 data bits, 1 stop bit, no parity, no flow control.
Received byte should be displayed on LED display in hexadecimal notation (choose any 2 consecutive digits on LED display, other digits should be disabled).

Inputs and outputs of the system:


clk_i - clock 50MHz,
rst_i asynchronous reset,

RXD_i - RS232 input,
led7_an_o anode output to LED display.

led7_seg_o segment output to LED display.

LED Display uses four 7-segment displays. You have to multiplex segment data with anode enable. 0 logic enables anode and segment. Suggested multiplexing frequency is 1kHz.

 



The circuit has to be verified experimentally by programming the FPGA on development board. You should also write the testbench and perform functional simulation. Show the results to the instructor. For testing use MINICOM terminal emulation program (MINICOM is by default configured as follows: 9600bps, 8 data bits, 1 stop bit, no parity).


Transmission and reception of data in RS232 standard:

Transmission and reception of RS232 signals is serial. When the line is idle logic level on the input and output line is 1. Beginning of the transmission is signaled by the falling edge of the input signal followed by 0 level lasting for 1/baud_rate seconds (where baud_rate is the speed parameter of RS232). In the example start bit (and all other bits) lasts for 1/9600 second each. Data bits follow start bit and are send serially LSB first. Then the optional parity bit can be sent (but it is not present in our example parity is disabled in the RS232 settings). The end of transmission is signaled by the stop bit which has logic level 1. Example of transmission of the code: 01010011 is presented below:

Transmisja RS-232
Fig.1 Transmission of the code: 01010011 using RS-232 (9600 bps, 8-bits, 1-stop, no parity).


Additional information about RS232:
http://www.fizyka.umk.pl/~ptarg/labview/folie/RS232.pdf
http://pl.wikipedia.org/wiki/RS-232


UCF file for the exercise (for Digilent Spartan-3 board, FPGA: Spartan-3 3S200 FT256-4):


# Clock:
NET "clk_i" LOC = "T9" ; # 50 MHz clock
# Push-buttons:
NET "rst_i" LOC = "L14" ; # pressed high BTN3
# RS232:
NET "RXD_i" LOC = "T13" ; # RS 232 RXD
# Seven-segment LED display:
NET "led7_an_o<3>" LOC = "E13" ; # leftmost digit, active low
NET "led7_an_o<2>" LOC = "F14" ; # active low
NET "led7_an_o<1>" LOC = "G14" ; # active low
NET "led7_an_o<0>" LOC = "D14" ; # rightmost digit, active low
#
NET "led7_seg_o<7>" LOC = "E14" ; # segment 'a', active low
NET "led7_seg_o<6>" LOC = "G13" ; # segment 'b', active low
NET "led7_seg_o<5>" LOC = "N15" ; # segment 'c', active low
NET "led7_seg_o<4>" LOC = "P15" ; # segment 'd', active low
NET "led7_seg_o<3>" LOC = "R16" ; # segment 'e', active low
NET "led7_seg_o<2>" LOC = "F13" ; # segment 'f', active low
NET "led7_seg_o<1>" LOC = "N16" ; # segment 'g', active low
NET "led7_seg_o<0>" LOC = "P16" ; # segment 'dp', active low
#