Sensor network research grant
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Department of Microelectronic Systems, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology Logo Wydziału

Sensor network for traffic monitoring

This work was supported in part by the Polish Ministry of Science and Higher Education under R&D grant no. R02 014 01.

Contents


Publications


Image recognition

Simulation results of blob recogniton:

EXPLANATION: frame,It, Klatka=input frame, BGs=selective background, BGs=non-selective background, mN=mask from non-selective background, mS=mask from non-selective background, mB=combined background mask, mE1,mET=temporal edges mask, mE2,mES=spatial edges mask, mH=highlights mask, mS=shadows mask, mHS=shadow and highlight mask, mV,Wynik=mask after final processing and Hough transform
NOTE: As initial background, the first frame is used. If the first frame contains moving object, it will be included in the background (e.g. in the sequence 'Speedway 7'). It may take some time the background will update correctly.

Experimental results:

Image layout:
input frame It μS μN mET mB
mS mN mHI mVtrans mET and mES
mES mV mET or mES mX mSH after erosion

Developed Software

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The main window of Sensor Network Simulator.

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Editing the parameters in Sensor Network Simulator.

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The assebler for the Pixel Processors.

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The main screen of Administration Software.

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The map view in of Administration Software.

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The traffic history view in Administration Software.

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The histograms illustrating the traffic flow.

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The mini histograms on the map view.

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The illustration of radio connectivity on the map view.

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The context menu for administration of the nodes.

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The picture downloaded from the node's camera.


FPGA Implementation

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The first prototype using prototyping board with Xilinx Virtex-4 FPGA and added cutom camera PCB.

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The PCB of the final FPGA prototype with Xilinx Virtex-4 FPGA.

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All FPGA prototype nodes ready for mounting on the street lamp poles.


ASIC

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The layout of the designed ASIC. Process: CMOS UMC 130nm.

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The picture of the manufactured die.

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The picture of the naked dies.

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The packed ASIC.

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The picture of the manufactured ASICs.


ASIC Implementation

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The PCBs of the ASIC prototype in production.

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The view of disassembled ASIC prototype.

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The ASIC prototype with attached service board for initial download of the bootloader software.

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The power supply part of the ASIC prototype's PCB with attached LCD display for monitoring power supply.

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The ASIC prototype without housing.

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Front view of ready ASIC prototype.


Installation on the street

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The nodes installed on the street.

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Installation of the nodes.

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Installation of the nodes.


Pictures of the installed nodes

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The node #109.

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The nodes #109 and #118.

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The node #118.

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The nodes #12, #16 and #120.

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The node #16.

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The nodes #12 and #120.

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The node #120.

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The node #10.

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The nodes #19 and #115.

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The node #115.

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The node #19.

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The node #22.

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The nodes #11 and #15.

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The nodes #11 and #15.

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The nodes #18, #21 and #24.

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The nodes #18, #21 and #24.

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The nodes #1, #2, #3, #4, #5 and #6.

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The nodes #1 and #2.

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The nodes #3 and #5.

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The nodes #4 and #6.

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The nodes #7 and #9.