---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:42:43 02/29/2012 -- Design Name: -- Module Name: dekoder_BCD - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dekoder_BCD is Port ( in_3 : in STD_LOGIC; in_2 : in STD_LOGIC; in_1 : in STD_LOGIC; in_0 : in STD_LOGIC; out_A : out STD_LOGIC; out_B : out STD_LOGIC; out_C : out STD_LOGIC; out_D : out STD_LOGIC; out_E : out STD_LOGIC; out_F : out STD_LOGIC; out_G : out STD_LOGIC; out_dot : out STD_LOGIC); end dekoder_BCD; architecture Behavioral of dekoder_BCD is signal sw_i : std_logic_vector (3 downto 0); signal lcd : std_logic_vector (7 downto 0); begin out_A <= lcd(7); out_B <= lcd(6); out_C <= lcd(5); out_D <= lcd(4); out_E <= lcd(3); out_F <= lcd(2); out_G <= lcd(1); out_dot <= lcd(0); sw_i <= (in_3 & in_2 & in_1 & in_0); with sw_i(3 downto 0) select lcd <= "00000011" when "0000", --0 "1000000" "10011111" when "0001", --1 "1111001" "00100101" when "0010", --2 "0100100" "00001101" when "0011", --3 "0110000" "10011001" when "0100", --4 "0011001" "01001001" when "0101", --5 "0010010" "01000001" when "0110", --6 "0000010" "00011111" when "0111", --7 "1111000" "00000001" when "1000", --8 "0000000" "00001001" when "1001", --9 "0010000" "00010001" when "1010", --A "0001000" "11000001" when "1011", --b "0000011" "01100011" when "1100", --C "1000110" "10000101" when "1101", --d "0100001" "01100001" when "1110", --E "0000110" "01110001" when "1111", --F "0001110" "11111110"when others; end Behavioral;