-- DCM: Digital Clock Manager Circuit
   -- Virtex-II/II-Pro and Spartan-3
   -- Xilinx HDL Language Template, version 10.1

   DCM_inst : DCM
   generic map (
      CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 5,   --  Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 12, --  Can be any integer from 1 to 32
      CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 0.0,          --  Specify period of input clock
      CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
      CLK_FEEDBACK => "NONE", --"1X",         --  Specify clock feedback of NONE, 1X or 2X
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             --     an integer from 0 to 15
      DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
      FACTORY_JF => X"C080",          --  FACTORY JF Values
      PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
      STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
   port map (
      CLK0 => open, --CLK0,     -- 0 degree DCM CLK ouptput
      CLK180 => open, --CLK180, -- 180 degree DCM CLK output
      CLK270 => open, --CLK270, -- 270 degree DCM CLK output
      CLK2X => open, --CLK2X,   -- 2X DCM CLK output
      CLK2X180 => open, --CLK2X180, -- 2X, 180 degree DCM CLK out
      CLK90 => open, --CLK90,   -- 90 degree DCM CLK output
      CLKDV => open, --CLKDV,   -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => CLKFX,   -- DCM CLK synthesis out (M/D)
      CLKFX180 => open, --CLKFX180, -- 180 degree CLK synthesis out
      LOCKED => open, --LOCKED, -- DCM LOCK status output
      PSDONE => open, --PSDONE, -- Dynamic phase adjust done output
      STATUS => open, --STATUS, -- 8-bit DCM status bits output
      CLKFB => '0', --CLKFB, -- DCM clock feedback
      CLKIN => clk_i, --CLKIN,   -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK => '0',--PSCLK, -- Dynamic phase adjust clock input
      PSEN => '0',--PSEN,   -- Dynamic phase adjust enable input
      PSINCDEC => '0',--PSINCDEC, -- Dynamic phase adjust increment/decrement
      RST => rst_i        -- DCM asynchronous reset input
   );

   -- End of DCM_inst instantiation