.ifndef INCLUDED_CYFITTERGNU_INC
.set INCLUDED_CYFITTERGNU_INC, 1
.include "cydevicegnu.inc"
.include "cydevicegnu_trm.inc"

/* LCD_LCDPort */
.set LCD_LCDPort__0__MASK, 0x01
.set LCD_LCDPort__0__PC, CYREG_PRT2_PC0
.set LCD_LCDPort__0__PORT, 2
.set LCD_LCDPort__0__SHIFT, 0
.set LCD_LCDPort__1__MASK, 0x02
.set LCD_LCDPort__1__PC, CYREG_PRT2_PC1
.set LCD_LCDPort__1__PORT, 2
.set LCD_LCDPort__1__SHIFT, 1
.set LCD_LCDPort__2__MASK, 0x04
.set LCD_LCDPort__2__PC, CYREG_PRT2_PC2
.set LCD_LCDPort__2__PORT, 2
.set LCD_LCDPort__2__SHIFT, 2
.set LCD_LCDPort__3__MASK, 0x08
.set LCD_LCDPort__3__PC, CYREG_PRT2_PC3
.set LCD_LCDPort__3__PORT, 2
.set LCD_LCDPort__3__SHIFT, 3
.set LCD_LCDPort__4__MASK, 0x10
.set LCD_LCDPort__4__PC, CYREG_PRT2_PC4
.set LCD_LCDPort__4__PORT, 2
.set LCD_LCDPort__4__SHIFT, 4
.set LCD_LCDPort__5__MASK, 0x20
.set LCD_LCDPort__5__PC, CYREG_PRT2_PC5
.set LCD_LCDPort__5__PORT, 2
.set LCD_LCDPort__5__SHIFT, 5
.set LCD_LCDPort__6__MASK, 0x40
.set LCD_LCDPort__6__PC, CYREG_PRT2_PC6
.set LCD_LCDPort__6__PORT, 2
.set LCD_LCDPort__6__SHIFT, 6
.set LCD_LCDPort__AG, CYREG_PRT2_AG
.set LCD_LCDPort__AMUX, CYREG_PRT2_AMUX
.set LCD_LCDPort__BIE, CYREG_PRT2_BIE
.set LCD_LCDPort__BIT_MASK, CYREG_PRT2_BIT_MASK
.set LCD_LCDPort__BYP, CYREG_PRT2_BYP
.set LCD_LCDPort__CTL, CYREG_PRT2_CTL
.set LCD_LCDPort__DM0, CYREG_PRT2_DM0
.set LCD_LCDPort__DM1, CYREG_PRT2_DM1
.set LCD_LCDPort__DM2, CYREG_PRT2_DM2
.set LCD_LCDPort__DR, CYREG_PRT2_DR
.set LCD_LCDPort__INP_DIS, CYREG_PRT2_INP_DIS
.set LCD_LCDPort__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set LCD_LCDPort__LCD_EN, CYREG_PRT2_LCD_EN
.set LCD_LCDPort__MASK, 0x7F
.set LCD_LCDPort__PORT, 2
.set LCD_LCDPort__PRT, CYREG_PRT2_PRT
.set LCD_LCDPort__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
.set LCD_LCDPort__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
.set LCD_LCDPort__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
.set LCD_LCDPort__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
.set LCD_LCDPort__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
.set LCD_LCDPort__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
.set LCD_LCDPort__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
.set LCD_LCDPort__PS, CYREG_PRT2_PS
.set LCD_LCDPort__SHIFT, 0
.set LCD_LCDPort__SLW, CYREG_PRT2_SLW

/* PWM_PWMUDB */
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
.set PWM_PWMUDB_genblk1_ctrlreg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set PWM_PWMUDB_genblk1_ctrlreg__7__MASK, 0x80
.set PWM_PWMUDB_genblk1_ctrlreg__7__POS, 7
.set PWM_PWMUDB_genblk1_ctrlreg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
.set PWM_PWMUDB_genblk1_ctrlreg__CONTROL_REG, CYREG_B1_UDB10_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__COUNT_REG, CYREG_B1_UDB10_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
.set PWM_PWMUDB_genblk1_ctrlreg__MASK, 0x80
.set PWM_PWMUDB_genblk1_ctrlreg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
.set PWM_PWMUDB_genblk1_ctrlreg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
.set PWM_PWMUDB_genblk1_ctrlreg__PERIOD_REG, CYREG_B1_UDB10_MSK
.set PWM_PWMUDB_genblk8_stsreg__0__MASK, 0x01
.set PWM_PWMUDB_genblk8_stsreg__0__POS, 0
.set PWM_PWMUDB_genblk8_stsreg__2__MASK, 0x04
.set PWM_PWMUDB_genblk8_stsreg__2__POS, 2
.set PWM_PWMUDB_genblk8_stsreg__3__MASK, 0x08
.set PWM_PWMUDB_genblk8_stsreg__3__POS, 3
.set PWM_PWMUDB_genblk8_stsreg__MASK, 0x0D
.set PWM_PWMUDB_genblk8_stsreg__MASK_REG, CYREG_B1_UDB11_MSK
.set PWM_PWMUDB_genblk8_stsreg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set PWM_PWMUDB_genblk8_stsreg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set PWM_PWMUDB_genblk8_stsreg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set PWM_PWMUDB_genblk8_stsreg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
.set PWM_PWMUDB_genblk8_stsreg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
.set PWM_PWMUDB_genblk8_stsreg__STATUS_REG, CYREG_B1_UDB11_ST
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_A0_REG, CYREG_B1_UDB10_11_A0
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_A1_REG, CYREG_B1_UDB10_11_A1
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_D0_REG, CYREG_B1_UDB10_11_D0
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_D1_REG, CYREG_B1_UDB10_11_D1
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_F0_REG, CYREG_B1_UDB10_11_F0
.set PWM_PWMUDB_sP16_pwmdp_u0__16BIT_F1_REG, CYREG_B1_UDB10_11_F1
.set PWM_PWMUDB_sP16_pwmdp_u0__A0_A1_REG, CYREG_B1_UDB10_A0_A1
.set PWM_PWMUDB_sP16_pwmdp_u0__A0_REG, CYREG_B1_UDB10_A0
.set PWM_PWMUDB_sP16_pwmdp_u0__A1_REG, CYREG_B1_UDB10_A1
.set PWM_PWMUDB_sP16_pwmdp_u0__D0_D1_REG, CYREG_B1_UDB10_D0_D1
.set PWM_PWMUDB_sP16_pwmdp_u0__D0_REG, CYREG_B1_UDB10_D0
.set PWM_PWMUDB_sP16_pwmdp_u0__D1_REG, CYREG_B1_UDB10_D1
.set PWM_PWMUDB_sP16_pwmdp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
.set PWM_PWMUDB_sP16_pwmdp_u0__F0_F1_REG, CYREG_B1_UDB10_F0_F1
.set PWM_PWMUDB_sP16_pwmdp_u0__F0_REG, CYREG_B1_UDB10_F0
.set PWM_PWMUDB_sP16_pwmdp_u0__F1_REG, CYREG_B1_UDB10_F1
.set PWM_PWMUDB_sP16_pwmdp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
.set PWM_PWMUDB_sP16_pwmdp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
.set PWM_PWMUDB_sP16_pwmdp_u1__A0_A1_REG, CYREG_B1_UDB11_A0_A1
.set PWM_PWMUDB_sP16_pwmdp_u1__A0_REG, CYREG_B1_UDB11_A0
.set PWM_PWMUDB_sP16_pwmdp_u1__A1_REG, CYREG_B1_UDB11_A1
.set PWM_PWMUDB_sP16_pwmdp_u1__D0_D1_REG, CYREG_B1_UDB11_D0_D1
.set PWM_PWMUDB_sP16_pwmdp_u1__D0_REG, CYREG_B1_UDB11_D0
.set PWM_PWMUDB_sP16_pwmdp_u1__D1_REG, CYREG_B1_UDB11_D1
.set PWM_PWMUDB_sP16_pwmdp_u1__DP_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set PWM_PWMUDB_sP16_pwmdp_u1__F0_F1_REG, CYREG_B1_UDB11_F0_F1
.set PWM_PWMUDB_sP16_pwmdp_u1__F0_REG, CYREG_B1_UDB11_F0
.set PWM_PWMUDB_sP16_pwmdp_u1__F1_REG, CYREG_B1_UDB11_F1
.set PWM_PWMUDB_sP16_pwmdp_u1__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set PWM_PWMUDB_sP16_pwmdp_u1__PER_DP_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL

/* LED3 */
.set LED3__0__MASK, 0x04
.set LED3__0__PC, CYREG_PRT6_PC2
.set LED3__0__PORT, 6
.set LED3__0__SHIFT, 2
.set LED3__AG, CYREG_PRT6_AG
.set LED3__AMUX, CYREG_PRT6_AMUX
.set LED3__BIE, CYREG_PRT6_BIE
.set LED3__BIT_MASK, CYREG_PRT6_BIT_MASK
.set LED3__BYP, CYREG_PRT6_BYP
.set LED3__CTL, CYREG_PRT6_CTL
.set LED3__DM0, CYREG_PRT6_DM0
.set LED3__DM1, CYREG_PRT6_DM1
.set LED3__DM2, CYREG_PRT6_DM2
.set LED3__DR, CYREG_PRT6_DR
.set LED3__INP_DIS, CYREG_PRT6_INP_DIS
.set LED3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set LED3__LCD_EN, CYREG_PRT6_LCD_EN
.set LED3__MASK, 0x04
.set LED3__PORT, 6
.set LED3__PRT, CYREG_PRT6_PRT
.set LED3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set LED3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set LED3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set LED3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set LED3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set LED3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set LED3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set LED3__PS, CYREG_PRT6_PS
.set LED3__SHIFT, 2
.set LED3__SLW, CYREG_PRT6_SLW

/* LED4 */
.set LED4__0__MASK, 0x08
.set LED4__0__PC, CYREG_PRT6_PC3
.set LED4__0__PORT, 6
.set LED4__0__SHIFT, 3
.set LED4__AG, CYREG_PRT6_AG
.set LED4__AMUX, CYREG_PRT6_AMUX
.set LED4__BIE, CYREG_PRT6_BIE
.set LED4__BIT_MASK, CYREG_PRT6_BIT_MASK
.set LED4__BYP, CYREG_PRT6_BYP
.set LED4__CTL, CYREG_PRT6_CTL
.set LED4__DM0, CYREG_PRT6_DM0
.set LED4__DM1, CYREG_PRT6_DM1
.set LED4__DM2, CYREG_PRT6_DM2
.set LED4__DR, CYREG_PRT6_DR
.set LED4__INP_DIS, CYREG_PRT6_INP_DIS
.set LED4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set LED4__LCD_EN, CYREG_PRT6_LCD_EN
.set LED4__MASK, 0x08
.set LED4__PORT, 6
.set LED4__PRT, CYREG_PRT6_PRT
.set LED4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set LED4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set LED4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set LED4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set LED4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set LED4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set LED4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set LED4__PS, CYREG_PRT6_PS
.set LED4__SHIFT, 3
.set LED4__SLW, CYREG_PRT6_SLW

/* CONTROL */
.set CONTROL_Sync_ctrl_reg__0__MASK, 0x01
.set CONTROL_Sync_ctrl_reg__0__POS, 0
.set CONTROL_Sync_ctrl_reg__1__MASK, 0x02
.set CONTROL_Sync_ctrl_reg__1__POS, 1
.set CONTROL_Sync_ctrl_reg__2__MASK, 0x04
.set CONTROL_Sync_ctrl_reg__2__POS, 2
.set CONTROL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set CONTROL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
.set CONTROL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
.set CONTROL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
.set CONTROL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
.set CONTROL_Sync_ctrl_reg__MASK, 0x07
.set CONTROL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set CONTROL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set CONTROL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK

/* Clock_1 */
.set Clock_1__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set Clock_1__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set Clock_1__CFG2, CYREG_CLKDIST_DCFG1_CFG2
.set Clock_1__CFG2_SRC_SEL_MASK, 0x07
.set Clock_1__INDEX, 0x01
.set Clock_1__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set Clock_1__PM_ACT_MSK, 0x02
.set Clock_1__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set Clock_1__PM_STBY_MSK, 0x02

/* CapSense_BufCH0 */
.set CapSense_BufCH0__CFG0, CYREG_CAPSL_CFG0
.set CapSense_BufCH0__CFG1, CYREG_CAPSL_CFG1
.set CapSense_BufCH0__PM_ACT_CFG, CYREG_PM_ACT_CFG11
.set CapSense_BufCH0__PM_ACT_MSK, 0x10
.set CapSense_BufCH0__PM_STBY_CFG, CYREG_PM_STBY_CFG11
.set CapSense_BufCH0__PM_STBY_MSK, 0x10

/* CapSense_ClockGen */
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
.set CapSense_ClockGen_sC16_PRSdp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
.set CapSense_ClockGen_sC16_PRSdp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
.set CapSense_ClockGen_sC16_PRSdp_u0__A0_REG, CYREG_B1_UDB04_A0
.set CapSense_ClockGen_sC16_PRSdp_u0__A1_REG, CYREG_B1_UDB04_A1
.set CapSense_ClockGen_sC16_PRSdp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
.set CapSense_ClockGen_sC16_PRSdp_u0__D0_REG, CYREG_B1_UDB04_D0
.set CapSense_ClockGen_sC16_PRSdp_u0__D1_REG, CYREG_B1_UDB04_D1
.set CapSense_ClockGen_sC16_PRSdp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set CapSense_ClockGen_sC16_PRSdp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
.set CapSense_ClockGen_sC16_PRSdp_u0__F0_REG, CYREG_B1_UDB04_F0
.set CapSense_ClockGen_sC16_PRSdp_u0__F1_REG, CYREG_B1_UDB04_F1
.set CapSense_ClockGen_sC16_PRSdp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set CapSense_ClockGen_sC16_PRSdp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_A0_REG, CYREG_B1_UDB05_06_A0
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_A1_REG, CYREG_B1_UDB05_06_A1
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_D0_REG, CYREG_B1_UDB05_06_D0
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_D1_REG, CYREG_B1_UDB05_06_D1
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_F0_REG, CYREG_B1_UDB05_06_F0
.set CapSense_ClockGen_sC16_PRSdp_u1__16BIT_F1_REG, CYREG_B1_UDB05_06_F1
.set CapSense_ClockGen_sC16_PRSdp_u1__A0_A1_REG, CYREG_B1_UDB05_A0_A1
.set CapSense_ClockGen_sC16_PRSdp_u1__A0_REG, CYREG_B1_UDB05_A0
.set CapSense_ClockGen_sC16_PRSdp_u1__A1_REG, CYREG_B1_UDB05_A1
.set CapSense_ClockGen_sC16_PRSdp_u1__D0_D1_REG, CYREG_B1_UDB05_D0_D1
.set CapSense_ClockGen_sC16_PRSdp_u1__D0_REG, CYREG_B1_UDB05_D0
.set CapSense_ClockGen_sC16_PRSdp_u1__D1_REG, CYREG_B1_UDB05_D1
.set CapSense_ClockGen_sC16_PRSdp_u1__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set CapSense_ClockGen_sC16_PRSdp_u1__F0_F1_REG, CYREG_B1_UDB05_F0_F1
.set CapSense_ClockGen_sC16_PRSdp_u1__F0_REG, CYREG_B1_UDB05_F0
.set CapSense_ClockGen_sC16_PRSdp_u1__F1_REG, CYREG_B1_UDB05_F1
.set CapSense_ClockGen_ScanSpeed__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set CapSense_ClockGen_ScanSpeed__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set CapSense_ClockGen_ScanSpeed__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set CapSense_ClockGen_ScanSpeed__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set CapSense_ClockGen_ScanSpeed__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set CapSense_ClockGen_ScanSpeed__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
.set CapSense_ClockGen_ScanSpeed__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set CapSense_ClockGen_ScanSpeed__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
.set CapSense_ClockGen_ScanSpeed__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set CapSense_ClockGen_ScanSpeed__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set CapSense_ClockGen_ScanSpeed__CONTROL_REG, CYREG_B0_UDB07_CTL
.set CapSense_ClockGen_ScanSpeed__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
.set CapSense_ClockGen_ScanSpeed__COUNT_REG, CYREG_B0_UDB07_CTL
.set CapSense_ClockGen_ScanSpeed__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
.set CapSense_ClockGen_ScanSpeed__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set CapSense_ClockGen_ScanSpeed__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set CapSense_ClockGen_ScanSpeed__PERIOD_REG, CYREG_B0_UDB07_MSK
.set CapSense_ClockGen_SyncCtrl_CtrlReg__0__MASK, 0x01
.set CapSense_ClockGen_SyncCtrl_CtrlReg__0__POS, 0
.set CapSense_ClockGen_SyncCtrl_CtrlReg__1__MASK, 0x02
.set CapSense_ClockGen_SyncCtrl_CtrlReg__1__POS, 1
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
.set CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
.set CapSense_ClockGen_SyncCtrl_CtrlReg__2__MASK, 0x04
.set CapSense_ClockGen_SyncCtrl_CtrlReg__2__POS, 2
.set CapSense_ClockGen_SyncCtrl_CtrlReg__4__MASK, 0x10
.set CapSense_ClockGen_SyncCtrl_CtrlReg__4__POS, 4
.set CapSense_ClockGen_SyncCtrl_CtrlReg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__CONTROL_REG, CYREG_B1_UDB04_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__COUNT_REG, CYREG_B1_UDB04_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__MASK, 0x17
.set CapSense_ClockGen_SyncCtrl_CtrlReg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set CapSense_ClockGen_SyncCtrl_CtrlReg__PERIOD_REG, CYREG_B1_UDB04_MSK
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
.set CapSense_ClockGen_UDB_PrescalerDp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__A0_REG, CYREG_B0_UDB06_A0
.set CapSense_ClockGen_UDB_PrescalerDp_u0__A1_REG, CYREG_B0_UDB06_A1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__D0_REG, CYREG_B0_UDB06_D0
.set CapSense_ClockGen_UDB_PrescalerDp_u0__D1_REG, CYREG_B0_UDB06_D1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set CapSense_ClockGen_UDB_PrescalerDp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
.set CapSense_ClockGen_UDB_PrescalerDp_u0__F0_REG, CYREG_B0_UDB06_F0
.set CapSense_ClockGen_UDB_PrescalerDp_u0__F1_REG, CYREG_B0_UDB06_F1

/* CapSense_CmodCH0 */
.set CapSense_CmodCH0__0__MASK, 0x10
.set CapSense_CmodCH0__0__PC, CYREG_PRT6_PC4
.set CapSense_CmodCH0__0__PORT, 6
.set CapSense_CmodCH0__0__SHIFT, 4
.set CapSense_CmodCH0__AG, CYREG_PRT6_AG
.set CapSense_CmodCH0__AMUX, CYREG_PRT6_AMUX
.set CapSense_CmodCH0__BIE, CYREG_PRT6_BIE
.set CapSense_CmodCH0__BIT_MASK, CYREG_PRT6_BIT_MASK
.set CapSense_CmodCH0__BYP, CYREG_PRT6_BYP
.set CapSense_CmodCH0__Cmod_CH0__MASK, 0x10
.set CapSense_CmodCH0__Cmod_CH0__PC, CYREG_PRT6_PC4
.set CapSense_CmodCH0__Cmod_CH0__PORT, 6
.set CapSense_CmodCH0__Cmod_CH0__SHIFT, 4
.set CapSense_CmodCH0__CTL, CYREG_PRT6_CTL
.set CapSense_CmodCH0__DM0, CYREG_PRT6_DM0
.set CapSense_CmodCH0__DM1, CYREG_PRT6_DM1
.set CapSense_CmodCH0__DM2, CYREG_PRT6_DM2
.set CapSense_CmodCH0__DR, CYREG_PRT6_DR
.set CapSense_CmodCH0__INP_DIS, CYREG_PRT6_INP_DIS
.set CapSense_CmodCH0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set CapSense_CmodCH0__LCD_EN, CYREG_PRT6_LCD_EN
.set CapSense_CmodCH0__MASK, 0x10
.set CapSense_CmodCH0__PORT, 6
.set CapSense_CmodCH0__PRT, CYREG_PRT6_PRT
.set CapSense_CmodCH0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set CapSense_CmodCH0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set CapSense_CmodCH0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set CapSense_CmodCH0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set CapSense_CmodCH0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set CapSense_CmodCH0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set CapSense_CmodCH0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set CapSense_CmodCH0__PS, CYREG_PRT6_PS
.set CapSense_CmodCH0__SHIFT, 4
.set CapSense_CmodCH0__SLW, CYREG_PRT6_SLW

/* CapSense_CompCH0_ctComp */
.set CapSense_CompCH0_ctComp__CLK, CYREG_CMP1_CLK
.set CapSense_CompCH0_ctComp__CMP_MASK, 0x02
.set CapSense_CompCH0_ctComp__CMP_NUMBER, 1
.set CapSense_CompCH0_ctComp__CR, CYREG_CMP1_CR
.set CapSense_CompCH0_ctComp__LUT__CR, CYREG_LUT1_CR
.set CapSense_CompCH0_ctComp__LUT__MSK, CYREG_LUT_MSK
.set CapSense_CompCH0_ctComp__LUT__MSK_MASK, 0x02
.set CapSense_CompCH0_ctComp__LUT__MSK_SHIFT, 1
.set CapSense_CompCH0_ctComp__LUT__MX, CYREG_LUT1_MX
.set CapSense_CompCH0_ctComp__LUT__SR, CYREG_LUT_SR
.set CapSense_CompCH0_ctComp__LUT__SR_MASK, 0x02
.set CapSense_CompCH0_ctComp__LUT__SR_SHIFT, 1
.set CapSense_CompCH0_ctComp__PM_ACT_CFG, CYREG_PM_ACT_CFG7
.set CapSense_CompCH0_ctComp__PM_ACT_MSK, 0x02
.set CapSense_CompCH0_ctComp__PM_STBY_CFG, CYREG_PM_STBY_CFG7
.set CapSense_CompCH0_ctComp__PM_STBY_MSK, 0x02
.set CapSense_CompCH0_ctComp__SW0, CYREG_CMP1_SW0
.set CapSense_CompCH0_ctComp__SW2, CYREG_CMP1_SW2
.set CapSense_CompCH0_ctComp__SW3, CYREG_CMP1_SW3
.set CapSense_CompCH0_ctComp__SW4, CYREG_CMP1_SW4
.set CapSense_CompCH0_ctComp__SW6, CYREG_CMP1_SW6
.set CapSense_CompCH0_ctComp__TR0, CYREG_CMP1_TR0
.set CapSense_CompCH0_ctComp__TR1, CYREG_CMP1_TR1
.set CapSense_CompCH0_ctComp__TRIM__TR0, CYREG_FLSHID_MFG_CFG_CMP1_TR0
.set CapSense_CompCH0_ctComp__TRIM__TR0_HS, CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS
.set CapSense_CompCH0_ctComp__TRIM__TR1, CYREG_FLSHID_MFG_CFG_CMP1_TR1
.set CapSense_CompCH0_ctComp__TRIM__TR1_HS, CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS
.set CapSense_CompCH0_ctComp__WRK, CYREG_CMP_WRK
.set CapSense_CompCH0_ctComp__WRK_MASK, 0x02
.set CapSense_CompCH0_ctComp__WRK_SHIFT, 1

/* CapSense_IdacCH0_viDAC8 */
.set CapSense_IdacCH0_viDAC8__CR0, CYREG_DAC3_CR0
.set CapSense_IdacCH0_viDAC8__CR1, CYREG_DAC3_CR1
.set CapSense_IdacCH0_viDAC8__D, CYREG_DAC3_D
.set CapSense_IdacCH0_viDAC8__PM_ACT_CFG, CYREG_PM_ACT_CFG8
.set CapSense_IdacCH0_viDAC8__PM_ACT_MSK, 0x08
.set CapSense_IdacCH0_viDAC8__PM_STBY_CFG, CYREG_PM_STBY_CFG8
.set CapSense_IdacCH0_viDAC8__PM_STBY_MSK, 0x08
.set CapSense_IdacCH0_viDAC8__STROBE, CYREG_DAC3_STROBE
.set CapSense_IdacCH0_viDAC8__SW0, CYREG_DAC3_SW0
.set CapSense_IdacCH0_viDAC8__SW2, CYREG_DAC3_SW2
.set CapSense_IdacCH0_viDAC8__SW3, CYREG_DAC3_SW3
.set CapSense_IdacCH0_viDAC8__SW4, CYREG_DAC3_SW4
.set CapSense_IdacCH0_viDAC8__TR, CYREG_DAC3_TR
.set CapSense_IdacCH0_viDAC8__TRIM__M1, CYREG_FLSHID_CUST_TABLES_DAC3_M1
.set CapSense_IdacCH0_viDAC8__TRIM__M2, CYREG_FLSHID_CUST_TABLES_DAC3_M2
.set CapSense_IdacCH0_viDAC8__TRIM__M3, CYREG_FLSHID_CUST_TABLES_DAC3_M3
.set CapSense_IdacCH0_viDAC8__TRIM__M4, CYREG_FLSHID_CUST_TABLES_DAC3_M4
.set CapSense_IdacCH0_viDAC8__TRIM__M5, CYREG_FLSHID_CUST_TABLES_DAC3_M5
.set CapSense_IdacCH0_viDAC8__TRIM__M6, CYREG_FLSHID_CUST_TABLES_DAC3_M6
.set CapSense_IdacCH0_viDAC8__TRIM__M7, CYREG_FLSHID_CUST_TABLES_DAC3_M7
.set CapSense_IdacCH0_viDAC8__TRIM__M8, CYREG_FLSHID_CUST_TABLES_DAC3_M8
.set CapSense_IdacCH0_viDAC8__TST, CYREG_DAC3_TST

/* CapSense_IntClock */
.set CapSense_IntClock__CFG0, CYREG_CLKDIST_DCFG0_CFG0
.set CapSense_IntClock__CFG1, CYREG_CLKDIST_DCFG0_CFG1
.set CapSense_IntClock__CFG2, CYREG_CLKDIST_DCFG0_CFG2
.set CapSense_IntClock__CFG2_SRC_SEL_MASK, 0x07
.set CapSense_IntClock__INDEX, 0x00
.set CapSense_IntClock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set CapSense_IntClock__PM_ACT_MSK, 0x01
.set CapSense_IntClock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set CapSense_IntClock__PM_STBY_MSK, 0x01

/* CapSense_IsrCH0 */
.set CapSense_IsrCH0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set CapSense_IsrCH0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set CapSense_IsrCH0__INTC_MASK, 0x01
.set CapSense_IsrCH0__INTC_NUMBER, 0
.set CapSense_IsrCH0__INTC_PRIOR_NUM, 7
.set CapSense_IsrCH0__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
.set CapSense_IsrCH0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set CapSense_IsrCH0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0

/* CapSense_MeasureCH0 */
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_A0_REG, CYREG_B1_UDB07_08_A0
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_A1_REG, CYREG_B1_UDB07_08_A1
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_D0_REG, CYREG_B1_UDB07_08_D0
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_D1_REG, CYREG_B1_UDB07_08_D1
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_F0_REG, CYREG_B1_UDB07_08_F0
.set CapSense_MeasureCH0_UDB_Counter_u0__16BIT_F1_REG, CYREG_B1_UDB07_08_F1
.set CapSense_MeasureCH0_UDB_Counter_u0__A0_A1_REG, CYREG_B1_UDB07_A0_A1
.set CapSense_MeasureCH0_UDB_Counter_u0__A0_REG, CYREG_B1_UDB07_A0
.set CapSense_MeasureCH0_UDB_Counter_u0__A1_REG, CYREG_B1_UDB07_A1
.set CapSense_MeasureCH0_UDB_Counter_u0__D0_D1_REG, CYREG_B1_UDB07_D0_D1
.set CapSense_MeasureCH0_UDB_Counter_u0__D0_REG, CYREG_B1_UDB07_D0
.set CapSense_MeasureCH0_UDB_Counter_u0__D1_REG, CYREG_B1_UDB07_D1
.set CapSense_MeasureCH0_UDB_Counter_u0__DP_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set CapSense_MeasureCH0_UDB_Counter_u0__F0_F1_REG, CYREG_B1_UDB07_F0_F1
.set CapSense_MeasureCH0_UDB_Counter_u0__F0_REG, CYREG_B1_UDB07_F0
.set CapSense_MeasureCH0_UDB_Counter_u0__F1_REG, CYREG_B1_UDB07_F1
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0
.set CapSense_MeasureCH0_UDB_Window_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1
.set CapSense_MeasureCH0_UDB_Window_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1
.set CapSense_MeasureCH0_UDB_Window_u0__A0_REG, CYREG_B1_UDB06_A0
.set CapSense_MeasureCH0_UDB_Window_u0__A1_REG, CYREG_B1_UDB06_A1
.set CapSense_MeasureCH0_UDB_Window_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1
.set CapSense_MeasureCH0_UDB_Window_u0__D0_REG, CYREG_B1_UDB06_D0
.set CapSense_MeasureCH0_UDB_Window_u0__D1_REG, CYREG_B1_UDB06_D1
.set CapSense_MeasureCH0_UDB_Window_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set CapSense_MeasureCH0_UDB_Window_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1
.set CapSense_MeasureCH0_UDB_Window_u0__F0_REG, CYREG_B1_UDB06_F0
.set CapSense_MeasureCH0_UDB_Window_u0__F1_REG, CYREG_B1_UDB06_F1

/* CapSense_PortCH0 */
.set CapSense_PortCH0__0__MASK, 0x20
.set CapSense_PortCH0__0__PC, CYREG_PRT5_PC5
.set CapSense_PortCH0__0__PORT, 5
.set CapSense_PortCH0__0__SHIFT, 5
.set CapSense_PortCH0__1__MASK, 0x40
.set CapSense_PortCH0__1__PC, CYREG_PRT5_PC6
.set CapSense_PortCH0__1__PORT, 5
.set CapSense_PortCH0__1__SHIFT, 6
.set CapSense_PortCH0__2__MASK, 0x01
.set CapSense_PortCH0__2__PC, CYREG_PRT5_PC0
.set CapSense_PortCH0__2__PORT, 5
.set CapSense_PortCH0__2__SHIFT, 0
.set CapSense_PortCH0__3__MASK, 0x02
.set CapSense_PortCH0__3__PC, CYREG_PRT5_PC1
.set CapSense_PortCH0__3__PORT, 5
.set CapSense_PortCH0__3__SHIFT, 1
.set CapSense_PortCH0__4__MASK, 0x04
.set CapSense_PortCH0__4__PC, CYREG_PRT5_PC2
.set CapSense_PortCH0__4__PORT, 5
.set CapSense_PortCH0__4__SHIFT, 2
.set CapSense_PortCH0__5__MASK, 0x08
.set CapSense_PortCH0__5__PC, CYREG_PRT5_PC3
.set CapSense_PortCH0__5__PORT, 5
.set CapSense_PortCH0__5__SHIFT, 3
.set CapSense_PortCH0__6__MASK, 0x10
.set CapSense_PortCH0__6__PC, CYREG_PRT5_PC4
.set CapSense_PortCH0__6__PORT, 5
.set CapSense_PortCH0__6__SHIFT, 4
.set CapSense_PortCH0__AG, CYREG_PRT5_AG
.set CapSense_PortCH0__AMUX, CYREG_PRT5_AMUX
.set CapSense_PortCH0__BIE, CYREG_PRT5_BIE
.set CapSense_PortCH0__BIT_MASK, CYREG_PRT5_BIT_MASK
.set CapSense_PortCH0__Button0__BTN__MASK, 0x40
.set CapSense_PortCH0__Button0__BTN__PC, CYREG_PRT5_PC6
.set CapSense_PortCH0__Button0__BTN__PORT, 5
.set CapSense_PortCH0__Button0__BTN__SHIFT, 6
.set CapSense_PortCH0__Button1__BTN__MASK, 0x20
.set CapSense_PortCH0__Button1__BTN__PC, CYREG_PRT5_PC5
.set CapSense_PortCH0__Button1__BTN__PORT, 5
.set CapSense_PortCH0__Button1__BTN__SHIFT, 5
.set CapSense_PortCH0__BYP, CYREG_PRT5_BYP
.set CapSense_PortCH0__CTL, CYREG_PRT5_CTL
.set CapSense_PortCH0__DM0, CYREG_PRT5_DM0
.set CapSense_PortCH0__DM1, CYREG_PRT5_DM1
.set CapSense_PortCH0__DM2, CYREG_PRT5_DM2
.set CapSense_PortCH0__DR, CYREG_PRT5_DR
.set CapSense_PortCH0__INP_DIS, CYREG_PRT5_INP_DIS
.set CapSense_PortCH0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set CapSense_PortCH0__LCD_EN, CYREG_PRT5_LCD_EN
.set CapSense_PortCH0__LinearSlider0_e0__LS__MASK, 0x01
.set CapSense_PortCH0__LinearSlider0_e0__LS__PC, CYREG_PRT5_PC0
.set CapSense_PortCH0__LinearSlider0_e0__LS__PORT, 5
.set CapSense_PortCH0__LinearSlider0_e0__LS__SHIFT, 0
.set CapSense_PortCH0__LinearSlider0_e1__LS__MASK, 0x02
.set CapSense_PortCH0__LinearSlider0_e1__LS__PC, CYREG_PRT5_PC1
.set CapSense_PortCH0__LinearSlider0_e1__LS__PORT, 5
.set CapSense_PortCH0__LinearSlider0_e1__LS__SHIFT, 1
.set CapSense_PortCH0__LinearSlider0_e2__LS__MASK, 0x04
.set CapSense_PortCH0__LinearSlider0_e2__LS__PC, CYREG_PRT5_PC2
.set CapSense_PortCH0__LinearSlider0_e2__LS__PORT, 5
.set CapSense_PortCH0__LinearSlider0_e2__LS__SHIFT, 2
.set CapSense_PortCH0__LinearSlider0_e3__LS__MASK, 0x08
.set CapSense_PortCH0__LinearSlider0_e3__LS__PC, CYREG_PRT5_PC3
.set CapSense_PortCH0__LinearSlider0_e3__LS__PORT, 5
.set CapSense_PortCH0__LinearSlider0_e3__LS__SHIFT, 3
.set CapSense_PortCH0__LinearSlider0_e4__LS__MASK, 0x10
.set CapSense_PortCH0__LinearSlider0_e4__LS__PC, CYREG_PRT5_PC4
.set CapSense_PortCH0__LinearSlider0_e4__LS__PORT, 5
.set CapSense_PortCH0__LinearSlider0_e4__LS__SHIFT, 4
.set CapSense_PortCH0__PORT, 5
.set CapSense_PortCH0__PRT, CYREG_PRT5_PRT
.set CapSense_PortCH0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
.set CapSense_PortCH0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
.set CapSense_PortCH0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
.set CapSense_PortCH0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
.set CapSense_PortCH0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
.set CapSense_PortCH0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set CapSense_PortCH0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set CapSense_PortCH0__PS, CYREG_PRT5_PS
.set CapSense_PortCH0__SLW, CYREG_PRT5_SLW

/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 24000000
.set BCLK__BUS_CLK__KHZ, 24000
.set BCLK__BUS_CLK__MHZ, 24
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PANTHER, 6
.set CYDEV_CHIP_DIE_PSOC4A, 3
.set CYDEV_CHIP_DIE_PSOC5LP, 5
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
.set CYDEV_CHIP_JTAG_ID, 0x2E123069
.set CYDEV_CHIP_MEMBER_3A, 1
.set CYDEV_CHIP_MEMBER_4A, 3
.set CYDEV_CHIP_MEMBER_4D, 2
.set CYDEV_CHIP_MEMBER_4F, 4
.set CYDEV_CHIP_MEMBER_5A, 6
.set CYDEV_CHIP_MEMBER_5B, 5
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
.set CYDEV_CHIP_REV_PANTHER_ES0, 0
.set CYDEV_CHIP_REV_PANTHER_ES1, 1
.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_DMA, 0
.set CYDEV_CONFIGURATION_ECC, 1
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
.set CYDEV_DEBUG_ENABLE_MASK, 0x20
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DEBUGGING_XRES, 0
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x80
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
.set CYDEV_INTR_RISING, 0x00000001
.set CYDEV_PROJ_TYPE, 0
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LOADABLE, 2
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_PROTECTION_ENABLE, 0
.set CYDEV_STACK_SIZE, 0x0800
.set CYDEV_USE_BUNDLED_CMSIS, 1
.set CYDEV_VARIABLE_VDDA, 0
.set CYDEV_VDDA_MV, 5000
.set CYDEV_VDDD_MV, 5000
.set CYDEV_VDDIO0_MV, 5000
.set CYDEV_VDDIO1_MV, 5000
.set CYDEV_VDDIO2_MV, 5000
.set CYDEV_VDDIO3_MV, 5000
.set CYDEV_VIO0_MV, 5000
.set CYDEV_VIO1_MV, 5000
.set CYDEV_VIO2_MV, 5000
.set CYDEV_VIO3_MV, 5000
.set CYIPBLOCK_ARM_CM3_VERSION, 0
.set CYIPBLOCK_P3_ANAIF_VERSION, 0
.set CYIPBLOCK_P3_CAN_VERSION, 0
.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
.set CYIPBLOCK_P3_COMP_VERSION, 0
.set CYIPBLOCK_P3_DECIMATOR_VERSION, 0
.set CYIPBLOCK_P3_DFB_VERSION, 0
.set CYIPBLOCK_P3_DMA_VERSION, 0
.set CYIPBLOCK_P3_DRQ_VERSION, 0
.set CYIPBLOCK_P3_DSM_VERSION, 0
.set CYIPBLOCK_P3_EMIF_VERSION, 0
.set CYIPBLOCK_P3_I2C_VERSION, 0
.set CYIPBLOCK_P3_LCD_VERSION, 0
.set CYIPBLOCK_P3_LPF_VERSION, 0
.set CYIPBLOCK_P3_OPAMP_VERSION, 0
.set CYIPBLOCK_P3_PM_VERSION, 0
.set CYIPBLOCK_P3_SCCT_VERSION, 0
.set CYIPBLOCK_P3_TIMER_VERSION, 0
.set CYIPBLOCK_P3_USB_VERSION, 0
.set CYIPBLOCK_P3_VIDAC_VERSION, 0
.set CYIPBLOCK_P3_VREF_VERSION, 0
.set CYIPBLOCK_S8_GPIO_VERSION, 0
.set CYIPBLOCK_S8_IRQ_VERSION, 0
.set CYIPBLOCK_S8_SAR_VERSION, 0
.set CYIPBLOCK_S8_SIO_VERSION, 0
.set CYIPBLOCK_S8_UDB_VERSION, 0
.set DMA_CHANNELS_USED__MASK0, 0x00000000
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
