# Static Timing Analysis

Project : | CapSense
Build Time : | 03/30/15 01:23:56
Device : | CY8C5868AXI-LP035
Temperature : | -40C - 85/125C
VDDA : | 5.00
VDDABUF : | 5.00
VDDD : | 5.00
VDDIO0 : | 5.00
VDDIO1 : | 5.00
VDDIO2 : | 5.00
VDDIO3 : | 5.00
VUSB : | 5.00
Voltage : | 5.0

Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CapSense_IntClock | CyMASTER_CLK | 12.000 MHz | 12.000 MHz | 42.299 MHz |
Clock_1 | CyMASTER_CLK | 12.000 MHz | 12.000 MHz | 43.344 MHz |
CyBUS_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CyPLL_OUT | CyPLL_OUT | 24.000 MHz | 24.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
+ Destination Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
Path Delay Requirement : 83.3333ns(12 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 42.299 MHz | 23.641 | 59.692 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_win_0\/main_0 | 2.603
macrocell12 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/main_0 | \CapSense:MeasureCH0:cs_addr_win_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 2.308
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 | 42.321 MHz | 23.629 | 59.704 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_cnt_1\/main_1 | 2.603
macrocell10 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_1\ | \CapSense:MeasureCH0:cs_addr_cnt_1\/main_1 | \CapSense:MeasureCH0:cs_addr_cnt_1\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_1\ | \CapSense:MeasureCH0:cs_addr_cnt_1\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 | 2.296
datapathcell4 | U(2,1) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 | 42.324 MHz | 23.627 | 59.706 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_cnt_0\/main_1 | 2.603
macrocell9 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_0\ | \CapSense:MeasureCH0:cs_addr_cnt_0\/main_1 | \CapSense:MeasureCH0:cs_addr_cnt_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_0\ | \CapSense:MeasureCH0:cs_addr_cnt_0\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 | 2.294
datapathcell4 | U(2,1) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 42.328 MHz | 23.625 | 59.708 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 | 2.603
macrocell11 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 2.292
datapathcell4 | U(2,1) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 42.335 MHz | 23.621 | 59.712 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_win_0\/main_1 | 2.613
macrocell12 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/main_1 | \CapSense:MeasureCH0:cs_addr_win_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 2.308
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 | 42.357 MHz | 23.609 | 59.724 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 | 2.613
macrocell10 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_1\ | \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 | \CapSense:MeasureCH0:cs_addr_cnt_1\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_1\ | \CapSense:MeasureCH0:cs_addr_cnt_1\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 | 2.296
datapathcell4 | U(2,1) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 | 42.360 MHz | 23.607 | 59.726 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 | 2.613
macrocell9 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_0\ | \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 | \CapSense:MeasureCH0:cs_addr_cnt_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_0\ | \CapSense:MeasureCH0:cs_addr_cnt_0\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 | 2.294
datapathcell4 | U(2,1) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 42.364 MHz | 23.605 | 59.728 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_2 | 2.613
macrocell11 | U(2,1) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_2 | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 2.292
datapathcell4 | U(2,1) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_2 | 42.821 MHz | 23.353 | 59.980 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_win_2\/main_0 | 2.303
macrocell14 | U(3,1) | 1 | \CapSense:MeasureCH0:cs_addr_win_2\ | \CapSense:MeasureCH0:cs_addr_win_2\/main_0 | \CapSense:MeasureCH0:cs_addr_win_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_2\ | \CapSense:MeasureCH0:cs_addr_win_2\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_2 | 2.320
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 | 42.836 MHz | 23.345 | 59.988 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_win_1\/main_0 | 2.303
macrocell13 | U(3,1) | 1 | \CapSense:MeasureCH0:cs_addr_win_1\ | \CapSense:MeasureCH0:cs_addr_win_1\/main_0 | \CapSense:MeasureCH0:cs_addr_win_1\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_1\ | \CapSense:MeasureCH0:cs_addr_win_1\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 | 2.312
datapathcell5 | U(3,1) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : Clock_1 : Positive edge(Required Frequency 12 MHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 12 MHz)
Path Delay Requirement : 83.3333ns(12 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 43.344 MHz | 23.071 | 60.262 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/clock | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | 2.320
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 2.960
Route |  | 1 | \PWM:PWMUDB:tc_i\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | 2.991
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | 9.710
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 46.209 MHz | 21.641 | 61.692 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/clock | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 3.850
Route |  | 1 | \PWM:PWMUDB:tc_i\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | 2.991
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | 9.710
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 | 50.525 MHz | 19.792 | 63.541 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/clock | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | 2.320
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 2.960
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 | 2.992
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | 50.528 MHz | 19.791 | 63.542 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/clock | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | 2.320
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 2.960
Route |  | 1 | \PWM:PWMUDB:tc_i\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | 2.991
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 52.829 MHz | 18.929 | 64.404 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell22 | U(1,0) | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/clock_0 | \PWM:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 | 2.879
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | 9.710
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 | 54.460 MHz | 18.362 | 64.971 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/clock | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 3.850
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 | 2.992
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | 54.463 MHz | 18.361 | 64.972 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/clock | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 3.850
Route |  | 1 | \PWM:PWMUDB:tc_i\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 | 2.991
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_1 | 63.375 MHz | 15.779 | 67.554 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell22 | U(1,0) | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/clock_0 | \PWM:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_1 | 3.009
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 | 63.902 MHz | 15.649 | 67.684 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell22 | U(1,0) | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/clock_0 | \PWM:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 | 2.879
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:genblk8:stsreg\/status_2 | 65.330 MHz | 15.307 | 68.026 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/clock | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | 2.320
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/z0 | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0i | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | 2.960
Route |  | 1 | \PWM:PWMUDB:tc_i\ | \PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb | \PWM:PWMUDB:status_2\/main_1 | 2.856
macrocell24 | U(1,0) | 1 | \PWM:PWMUDB:status_2\ | \PWM:PWMUDB:status_2\/main_1 | \PWM:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM:PWMUDB:status_2\ | \PWM:PWMUDB:status_2\/q | \PWM:PWMUDB:genblk8:stsreg\/status_2 | 2.251
statusicell1 | U(1,0) | 1 | \PWM:PWMUDB:genblk8:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : CapSense_IntClock : Positive edge
+ Destination Clock : CapSense_IntClock : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\CapSense:ClockGen:sC16:PRSdp:u1\/cmsbo | \CapSense:ClockGen:sC16:PRSdp:u0\/cmsbi | 2.250 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell3 | U(3,0) | 1 | \CapSense:ClockGen:sC16:PRSdp:u1\ | \CapSense:ClockGen:sC16:PRSdp:u1\/clock | \CapSense:ClockGen:sC16:PRSdp:u1\/cmsbo | 2.250
Route |  | 1 | \CapSense:ClockGen:sC16:PRSdp:u1.cmsbo__sig\ | \CapSense:ClockGen:sC16:PRSdp:u1\/cmsbo | \CapSense:ClockGen:sC16:PRSdp:u0\/cmsbi | 0.000
datapathcell2 | U(2,0) | 1 | \CapSense:ClockGen:sC16:PRSdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:tmp_ppulse_dly\/q | \CapSense:ClockGen:clock_detect_reg\/main_1 | 3.479 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell7 | U(2,0) | 1 | \CapSense:ClockGen:tmp_ppulse_dly\ | \CapSense:ClockGen:tmp_ppulse_dly\/clock_0 | \CapSense:ClockGen:tmp_ppulse_dly\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:tmp_ppulse_dly\ | \CapSense:ClockGen:tmp_ppulse_dly\/q | \CapSense:ClockGen:clock_detect_reg\/main_1 | 2.229
macrocell4 | U(2,0) | 1 | \CapSense:ClockGen:clock_detect_reg\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:wndState_0\/q | \CapSense:MeasureCH0:wndState_0\/main_3 | 3.484 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell15 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_0\ | \CapSense:MeasureCH0:wndState_0\/clock_0 | \CapSense:MeasureCH0:wndState_0\/q | 1.250
macrocell15 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_0\ | \CapSense:MeasureCH0:wndState_0\/q | \CapSense:MeasureCH0:wndState_0\/main_3 | 2.234
macrocell15 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:wndState_0\/q | \CapSense:MeasureCH0:wndState_2\/main_4 | 3.484 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell15 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_0\ | \CapSense:MeasureCH0:wndState_0\/clock_0 | \CapSense:MeasureCH0:wndState_0\/q | 1.250
Route |  | 1 | \CapSense:MeasureCH0:wndState_0\ | \CapSense:MeasureCH0:wndState_0\/q | \CapSense:MeasureCH0:wndState_2\/main_4 | 2.234
macrocell17 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:sC16:PRSdp:u0\/sol_msb | \CapSense:ClockGen:sC16:PRSdp:u1\/sir | 3.780 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(2,0) | 1 | \CapSense:ClockGen:sC16:PRSdp:u0\ | \CapSense:ClockGen:sC16:PRSdp:u0\/clock | \CapSense:ClockGen:sC16:PRSdp:u0\/sol_msb | 3.780
Route |  | 1 | \CapSense:ClockGen:sC16:PRSdp:u0.sol_msb__sig\ | \CapSense:ClockGen:sC16:PRSdp:u0\/sol_msb | \CapSense:ClockGen:sC16:PRSdp:u1\/sir | 0.000
datapathcell3 | U(3,0) | 1 | \CapSense:ClockGen:sC16:PRSdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:wndState_2\/q | \CapSense:MeasureCH0:wndState_0\/main_1 | 3.794 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell17 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_2\ | \CapSense:MeasureCH0:wndState_2\/clock_0 | \CapSense:MeasureCH0:wndState_2\/q | 1.250
Route |  | 1 | \CapSense:MeasureCH0:wndState_2\ | \CapSense:MeasureCH0:wndState_2\/q | \CapSense:MeasureCH0:wndState_0\/main_1 | 2.544
macrocell15 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:wndState_2\/q | \CapSense:MeasureCH0:wndState_2\/main_2 | 3.794 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell17 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_2\ | \CapSense:MeasureCH0:wndState_2\/clock_0 | \CapSense:MeasureCH0:wndState_2\/q | 1.250
macrocell17 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_2\ | \CapSense:MeasureCH0:wndState_2\/q | \CapSense:MeasureCH0:wndState_2\/main_2 | 2.544
macrocell17 | U(2,0) | 1 | \CapSense:MeasureCH0:wndState_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:wndState_1\/q | \CapSense:MeasureCH0:wndState_1\/main_5 | 3.888 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell16 | U(2,1) | 1 | \CapSense:MeasureCH0:wndState_1\ | \CapSense:MeasureCH0:wndState_1\/clock_0 | \CapSense:MeasureCH0:wndState_1\/q | 1.250
macrocell16 | U(2,1) | 1 | \CapSense:MeasureCH0:wndState_1\ | \CapSense:MeasureCH0:wndState_1\/q | \CapSense:MeasureCH0:wndState_1\/main_5 | 2.638
macrocell16 | U(2,1) | 1 | \CapSense:MeasureCH0:wndState_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:wndState_1\/q | \CapSense:Net_1603\/main_4 | 3.888 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell16 | U(2,1) | 1 | \CapSense:MeasureCH0:wndState_1\ | \CapSense:MeasureCH0:wndState_1\/clock_0 | \CapSense:MeasureCH0:wndState_1\/q | 1.250
Route |  | 1 | \CapSense:MeasureCH0:wndState_1\ | \CapSense:MeasureCH0:wndState_1\/q | \CapSense:Net_1603\/main_4 | 2.638
macrocell18 | U(2,1) | 1 | \CapSense:Net_1603\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:cstate_2\/q | \CapSense:ClockGen:cstate_2\/main_4 | 3.942 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell5 | U(2,0) | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/clock_0 | \CapSense:ClockGen:cstate_2\/q | 1.250
macrocell5 | U(2,0) | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/q | \CapSense:ClockGen:cstate_2\/main_4 | 2.692
macrocell5 | U(2,0) | 1 | \CapSense:ClockGen:cstate_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : Clock_1 : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\PWM:PWMUDB:status_0\/q | \PWM:PWMUDB:genblk8:stsreg\/status_0 | 1.494 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell23 | U(1,0) | 1 | \PWM:PWMUDB:status_0\ | \PWM:PWMUDB:status_0\/clock_0 | \PWM:PWMUDB:status_0\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:status_0\ | \PWM:PWMUDB:status_0\/q | \PWM:PWMUDB:genblk8:stsreg\/status_0 | 2.244
statusicell1 | U(1,0) | 1 | \PWM:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 3.210 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ | \PWM:PWMUDB:sP16:pwmdp:u0\/clock | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | 3.210
Route |  | 1 | \PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ | \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb | \PWM:PWMUDB:sP16:pwmdp:u1\/ci | 0.000
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:prevCompare1\/q | \PWM:PWMUDB:status_0\/main_0 | 3.478 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell21 | U(1,0) | 1 | \PWM:PWMUDB:prevCompare1\ | \PWM:PWMUDB:prevCompare1\/clock_0 | \PWM:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:prevCompare1\ | \PWM:PWMUDB:prevCompare1\/q | \PWM:PWMUDB:status_0\/main_0 | 2.228
macrocell23 | U(1,0) | 1 | \PWM:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 | 4.129 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell22 | U(1,0) | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/clock_0 | \PWM:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 | 2.879
datapathcell6 | U(0,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_1 | 4.259 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell22 | U(1,0) | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/clock_0 | \PWM:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM:PWMUDB:runmode_enable\ | \PWM:PWMUDB:runmode_enable\/q | \PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_1 | 3.009
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:genblk1:ctrlreg\/control_7 | Net_2248/main_0 | 4.316 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell3 | U(0,0) | 1 | \PWM:PWMUDB:genblk1:ctrlreg\ | \PWM:PWMUDB:genblk1:ctrlreg\/clock | \PWM:PWMUDB:genblk1:ctrlreg\/control_7 | 2.040
Route |  | 1 | \PWM:PWMUDB:control_7\ | \PWM:PWMUDB:genblk1:ctrlreg\/control_7 | Net_2248/main_0 | 2.276
macrocell1 | U(1,0) | 1 | Net_2248 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM:PWMUDB:runmode_enable\/main_0 | 4.316 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell3 | U(0,0) | 1 | \PWM:PWMUDB:genblk1:ctrlreg\ | \PWM:PWMUDB:genblk1:ctrlreg\/clock | \PWM:PWMUDB:genblk1:ctrlreg\/control_7 | 2.040
Route |  | 1 | \PWM:PWMUDB:control_7\ | \PWM:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM:PWMUDB:runmode_enable\/main_0 | 2.276
macrocell22 | U(1,0) | 1 | \PWM:PWMUDB:runmode_enable\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | \PWM:PWMUDB:status_0\/main_1 | 5.659 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/clock | \PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | 3.130
Route |  | 1 | \PWM:PWMUDB:cmp1_less\ | \PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | \PWM:PWMUDB:status_0\/main_1 | 2.529
macrocell23 | U(1,0) | 1 | \PWM:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | Net_2248/main_1 | 5.671 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/clock | \PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | 3.130
Route |  | 1 | \PWM:PWMUDB:cmp1_less\ | \PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | Net_2248/main_1 | 2.541
macrocell1 | U(1,0) | 1 | Net_2248 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | \PWM:PWMUDB:prevCompare1\/main_0 | 5.671 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell7 | U(1,0) | 1 | \PWM:PWMUDB:sP16:pwmdp:u1\ | \PWM:PWMUDB:sP16:pwmdp:u1\/clock | \PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | 3.130
Route |  | 1 | \PWM:PWMUDB:cmp1_less\ | \PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb | \PWM:PWMUDB:prevCompare1\/main_0 | 2.541
macrocell21 | U(1,0) | 1 | \PWM:PWMUDB:prevCompare1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Clock To Output Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
Net_2248/q | LED3(0)_PAD | 32.083

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell1 | U(1,0) | 1 | Net_2248 | Net_2248/clock_0 | Net_2248/q | 1.250
Route |  | 1 | Net_2248 | Net_2248/q | Net_2653/main_2 | 2.241
macrocell3 | U(1,0) | 1 | Net_2653 | Net_2653/main_2 | Net_2653/q | 3.350
Route |  | 1 | Net_2653 | Net_2653/q | LED3(0)/pin_input | 9.496
iocell1 | P6[2] | 1 | LED3(0) | LED3(0)/pin_input | LED3(0)/pad_out | 15.746
Route |  | 1 | LED3(0)_PAD | LED3(0)/pad_out | LED3(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

Net_2248/q | LED4(0)_PAD | 30.038

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell1 | U(1,0) | 1 | Net_2248 | Net_2248/clock_0 | Net_2248/q | 1.250
Route |  | 1 | Net_2248 | Net_2248/q | Net_2652/main_2 | 2.241
macrocell2 | U(1,0) | 1 | Net_2652 | Net_2652/main_2 | Net_2652/q | 3.350
Route |  | 1 | Net_2652 | Net_2652/q | LED4(0)/pin_input | 8.186
iocell2 | P6[3] | 1 | LED4(0) | LED4(0)/pin_input | LED4(0)/pad_out | 15.011
Route |  | 1 | LED4(0)_PAD | LED4(0)/pad_out | LED4(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

+ CyBUS_CLK

Source | Destination | Delay (ns)
--- | --- | ---
\CONTROL:Sync:ctrl_reg\/control_2 | LED3(0)_PAD | 33.419

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(1,0) | 1 | \CONTROL:Sync:ctrl_reg\ | \CONTROL:Sync:ctrl_reg\/busclk | \CONTROL:Sync:ctrl_reg\/control_2 | 2.580
Route |  | 1 | Net_2880 | \CONTROL:Sync:ctrl_reg\/control_2 | Net_2653/main_1 | 2.247
macrocell3 | U(1,0) | 1 | Net_2653 | Net_2653/main_1 | Net_2653/q | 3.350
Route |  | 1 | Net_2653 | Net_2653/q | LED3(0)/pin_input | 9.496
iocell1 | P6[2] | 1 | LED3(0) | LED3(0)/pin_input | LED3(0)/pad_out | 15.746
Route |  | 1 | LED3(0)_PAD | LED3(0)/pad_out | LED3(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

\CONTROL:Sync:ctrl_reg\/control_2 | LED4(0)_PAD | 31.374

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(1,0) | 1 | \CONTROL:Sync:ctrl_reg\ | \CONTROL:Sync:ctrl_reg\/busclk | \CONTROL:Sync:ctrl_reg\/control_2 | 2.580
Route |  | 1 | Net_2880 | \CONTROL:Sync:ctrl_reg\/control_2 | Net_2652/main_1 | 2.247
macrocell2 | U(1,0) | 1 | Net_2652 | Net_2652/main_1 | Net_2652/q | 3.350
Route |  | 1 | Net_2652 | Net_2652/q | LED4(0)/pin_input | 8.186
iocell2 | P6[3] | 1 | LED4(0) | LED4(0)/pin_input | LED4(0)/pad_out | 15.011
Route |  | 1 | LED4(0)_PAD | LED4(0)/pad_out | LED4(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

+ Asynchronous Constraints
+ Recovery
+ Source Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
+ Destination Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
Path Delay Requirement : 83.3333ns(12 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 108.483 MHz | 9.218 | 74.115 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell6 | U(2,0) | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/clock_0 | \CapSense:ClockGen:inter_reset\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 7.968
count7cell | U(2,2) | 1 | \CapSense:ClockGen:ScanSpeed\ |  | RECOVERY | -0.000
Clock |  |  |  |  | Skew | 0.000

+ Removal
+ Source Clock : CapSense_IntClock : Positive edge
+ Destination Clock : CapSense_IntClock : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 9.218 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell6 | U(2,0) | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/clock_0 | \CapSense:ClockGen:inter_reset\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 7.968
count7cell | U(2,2) | 1 | \CapSense:ClockGen:ScanSpeed\ |  | REMOVAL | 0.000
Clock |  |  |  |  | Skew | 0.000