#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include <cydevice.h>
#include <cydevice_trm.h>

/* LCD_LCDPort */
#define LCD_LCDPort__0__MASK 0x01u
#define LCD_LCDPort__0__PC CYREG_PRT2_PC0
#define LCD_LCDPort__0__PORT 2u
#define LCD_LCDPort__0__SHIFT 0
#define LCD_LCDPort__1__MASK 0x02u
#define LCD_LCDPort__1__PC CYREG_PRT2_PC1
#define LCD_LCDPort__1__PORT 2u
#define LCD_LCDPort__1__SHIFT 1
#define LCD_LCDPort__2__MASK 0x04u
#define LCD_LCDPort__2__PC CYREG_PRT2_PC2
#define LCD_LCDPort__2__PORT 2u
#define LCD_LCDPort__2__SHIFT 2
#define LCD_LCDPort__3__MASK 0x08u
#define LCD_LCDPort__3__PC CYREG_PRT2_PC3
#define LCD_LCDPort__3__PORT 2u
#define LCD_LCDPort__3__SHIFT 3
#define LCD_LCDPort__4__MASK 0x10u
#define LCD_LCDPort__4__PC CYREG_PRT2_PC4
#define LCD_LCDPort__4__PORT 2u
#define LCD_LCDPort__4__SHIFT 4
#define LCD_LCDPort__5__MASK 0x20u
#define LCD_LCDPort__5__PC CYREG_PRT2_PC5
#define LCD_LCDPort__5__PORT 2u
#define LCD_LCDPort__5__SHIFT 5
#define LCD_LCDPort__6__MASK 0x40u
#define LCD_LCDPort__6__PC CYREG_PRT2_PC6
#define LCD_LCDPort__6__PORT 2u
#define LCD_LCDPort__6__SHIFT 6
#define LCD_LCDPort__AG CYREG_PRT2_AG
#define LCD_LCDPort__AMUX CYREG_PRT2_AMUX
#define LCD_LCDPort__BIE CYREG_PRT2_BIE
#define LCD_LCDPort__BIT_MASK CYREG_PRT2_BIT_MASK
#define LCD_LCDPort__BYP CYREG_PRT2_BYP
#define LCD_LCDPort__CTL CYREG_PRT2_CTL
#define LCD_LCDPort__DM0 CYREG_PRT2_DM0
#define LCD_LCDPort__DM1 CYREG_PRT2_DM1
#define LCD_LCDPort__DM2 CYREG_PRT2_DM2
#define LCD_LCDPort__DR CYREG_PRT2_DR
#define LCD_LCDPort__INP_DIS CYREG_PRT2_INP_DIS
#define LCD_LCDPort__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define LCD_LCDPort__LCD_EN CYREG_PRT2_LCD_EN
#define LCD_LCDPort__MASK 0x7Fu
#define LCD_LCDPort__PORT 2u
#define LCD_LCDPort__PRT CYREG_PRT2_PRT
#define LCD_LCDPort__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define LCD_LCDPort__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define LCD_LCDPort__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define LCD_LCDPort__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define LCD_LCDPort__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define LCD_LCDPort__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define LCD_LCDPort__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define LCD_LCDPort__PS CYREG_PRT2_PS
#define LCD_LCDPort__SHIFT 0
#define LCD_LCDPort__SLW CYREG_PRT2_SLW

/* LED3 */
#define LED3__0__MASK 0x08u
#define LED3__0__PC CYREG_PRT6_PC3
#define LED3__0__PORT 6u
#define LED3__0__SHIFT 3
#define LED3__AG CYREG_PRT6_AG
#define LED3__AMUX CYREG_PRT6_AMUX
#define LED3__BIE CYREG_PRT6_BIE
#define LED3__BIT_MASK CYREG_PRT6_BIT_MASK
#define LED3__BYP CYREG_PRT6_BYP
#define LED3__CTL CYREG_PRT6_CTL
#define LED3__DM0 CYREG_PRT6_DM0
#define LED3__DM1 CYREG_PRT6_DM1
#define LED3__DM2 CYREG_PRT6_DM2
#define LED3__DR CYREG_PRT6_DR
#define LED3__INP_DIS CYREG_PRT6_INP_DIS
#define LED3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define LED3__LCD_EN CYREG_PRT6_LCD_EN
#define LED3__MASK 0x08u
#define LED3__PORT 6u
#define LED3__PRT CYREG_PRT6_PRT
#define LED3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define LED3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define LED3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define LED3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define LED3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define LED3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define LED3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define LED3__PS CYREG_PRT6_PS
#define LED3__SHIFT 3
#define LED3__SLW CYREG_PRT6_SLW

/* LED4 */
#define LED4__0__MASK 0x04u
#define LED4__0__PC CYREG_PRT6_PC2
#define LED4__0__PORT 6u
#define LED4__0__SHIFT 2
#define LED4__AG CYREG_PRT6_AG
#define LED4__AMUX CYREG_PRT6_AMUX
#define LED4__BIE CYREG_PRT6_BIE
#define LED4__BIT_MASK CYREG_PRT6_BIT_MASK
#define LED4__BYP CYREG_PRT6_BYP
#define LED4__CTL CYREG_PRT6_CTL
#define LED4__DM0 CYREG_PRT6_DM0
#define LED4__DM1 CYREG_PRT6_DM1
#define LED4__DM2 CYREG_PRT6_DM2
#define LED4__DR CYREG_PRT6_DR
#define LED4__INP_DIS CYREG_PRT6_INP_DIS
#define LED4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define LED4__LCD_EN CYREG_PRT6_LCD_EN
#define LED4__MASK 0x04u
#define LED4__PORT 6u
#define LED4__PRT CYREG_PRT6_PRT
#define LED4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define LED4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define LED4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define LED4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define LED4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define LED4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define LED4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define LED4__PS CYREG_PRT6_PS
#define LED4__SHIFT 2
#define LED4__SLW CYREG_PRT6_SLW

/* CapSense_BufCH0 */
#define CapSense_BufCH0__CFG0 CYREG_CAPSL_CFG0
#define CapSense_BufCH0__CFG1 CYREG_CAPSL_CFG1
#define CapSense_BufCH0__PM_ACT_CFG CYREG_PM_ACT_CFG11
#define CapSense_BufCH0__PM_ACT_MSK 0x10u
#define CapSense_BufCH0__PM_STBY_CFG CYREG_PM_STBY_CFG11
#define CapSense_BufCH0__PM_STBY_MSK 0x10u

/* CapSense_ClockGen */
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_A0_REG CYREG_B0_UDB10_11_A0
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_A1_REG CYREG_B0_UDB10_11_A1
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_D0_REG CYREG_B0_UDB10_11_D0
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_D1_REG CYREG_B0_UDB10_11_D1
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_F0_REG CYREG_B0_UDB10_11_F0
#define CapSense_ClockGen_sC16_PRSdp_u0__16BIT_F1_REG CYREG_B0_UDB10_11_F1
#define CapSense_ClockGen_sC16_PRSdp_u0__A0_A1_REG CYREG_B0_UDB10_A0_A1
#define CapSense_ClockGen_sC16_PRSdp_u0__A0_REG CYREG_B0_UDB10_A0
#define CapSense_ClockGen_sC16_PRSdp_u0__A1_REG CYREG_B0_UDB10_A1
#define CapSense_ClockGen_sC16_PRSdp_u0__D0_D1_REG CYREG_B0_UDB10_D0_D1
#define CapSense_ClockGen_sC16_PRSdp_u0__D0_REG CYREG_B0_UDB10_D0
#define CapSense_ClockGen_sC16_PRSdp_u0__D1_REG CYREG_B0_UDB10_D1
#define CapSense_ClockGen_sC16_PRSdp_u0__DP_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u0__F0_F1_REG CYREG_B0_UDB10_F0_F1
#define CapSense_ClockGen_sC16_PRSdp_u0__F0_REG CYREG_B0_UDB10_F0
#define CapSense_ClockGen_sC16_PRSdp_u0__F1_REG CYREG_B0_UDB10_F1
#define CapSense_ClockGen_sC16_PRSdp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_A0_REG CYREG_B0_UDB11_12_A0
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_A1_REG CYREG_B0_UDB11_12_A1
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_D0_REG CYREG_B0_UDB11_12_D0
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_D1_REG CYREG_B0_UDB11_12_D1
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_F0_REG CYREG_B0_UDB11_12_F0
#define CapSense_ClockGen_sC16_PRSdp_u1__16BIT_F1_REG CYREG_B0_UDB11_12_F1
#define CapSense_ClockGen_sC16_PRSdp_u1__A0_A1_REG CYREG_B0_UDB11_A0_A1
#define CapSense_ClockGen_sC16_PRSdp_u1__A0_REG CYREG_B0_UDB11_A0
#define CapSense_ClockGen_sC16_PRSdp_u1__A1_REG CYREG_B0_UDB11_A1
#define CapSense_ClockGen_sC16_PRSdp_u1__D0_D1_REG CYREG_B0_UDB11_D0_D1
#define CapSense_ClockGen_sC16_PRSdp_u1__D0_REG CYREG_B0_UDB11_D0
#define CapSense_ClockGen_sC16_PRSdp_u1__D1_REG CYREG_B0_UDB11_D1
#define CapSense_ClockGen_sC16_PRSdp_u1__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u1__F0_F1_REG CYREG_B0_UDB11_F0_F1
#define CapSense_ClockGen_sC16_PRSdp_u1__F0_REG CYREG_B0_UDB11_F0
#define CapSense_ClockGen_sC16_PRSdp_u1__F1_REG CYREG_B0_UDB11_F1
#define CapSense_ClockGen_sC16_PRSdp_u1__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define CapSense_ClockGen_sC16_PRSdp_u1__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define CapSense_ClockGen_ScanSpeed__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define CapSense_ClockGen_ScanSpeed__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define CapSense_ClockGen_ScanSpeed__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
#define CapSense_ClockGen_ScanSpeed__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define CapSense_ClockGen_ScanSpeed__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
#define CapSense_ClockGen_ScanSpeed__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
#define CapSense_ClockGen_ScanSpeed__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define CapSense_ClockGen_ScanSpeed__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
#define CapSense_ClockGen_ScanSpeed__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define CapSense_ClockGen_ScanSpeed__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define CapSense_ClockGen_ScanSpeed__CONTROL_REG CYREG_B0_UDB11_CTL
#define CapSense_ClockGen_ScanSpeed__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
#define CapSense_ClockGen_ScanSpeed__COUNT_REG CYREG_B0_UDB11_CTL
#define CapSense_ClockGen_ScanSpeed__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define CapSense_ClockGen_ScanSpeed__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define CapSense_ClockGen_ScanSpeed__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define CapSense_ClockGen_ScanSpeed__PERIOD_REG CYREG_B0_UDB11_MSK
#define CapSense_ClockGen_SyncCtrl_CtrlReg__0__MASK 0x01u
#define CapSense_ClockGen_SyncCtrl_CtrlReg__0__POS 0
#define CapSense_ClockGen_SyncCtrl_CtrlReg__1__MASK 0x02u
#define CapSense_ClockGen_SyncCtrl_CtrlReg__1__POS 1
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define CapSense_ClockGen_SyncCtrl_CtrlReg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define CapSense_ClockGen_SyncCtrl_CtrlReg__2__MASK 0x04u
#define CapSense_ClockGen_SyncCtrl_CtrlReg__2__POS 2
#define CapSense_ClockGen_SyncCtrl_CtrlReg__4__MASK 0x10u
#define CapSense_ClockGen_SyncCtrl_CtrlReg__4__POS 4
#define CapSense_ClockGen_SyncCtrl_CtrlReg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__CONTROL_REG CYREG_B0_UDB10_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__COUNT_REG CYREG_B0_UDB10_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__MASK 0x17u
#define CapSense_ClockGen_SyncCtrl_CtrlReg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define CapSense_ClockGen_SyncCtrl_CtrlReg__PERIOD_REG CYREG_B0_UDB10_MSK
#define CapSense_ClockGen_UDB_PrescalerDp_u0__A0_A1_REG CYREG_B0_UDB15_A0_A1
#define CapSense_ClockGen_UDB_PrescalerDp_u0__A0_REG CYREG_B0_UDB15_A0
#define CapSense_ClockGen_UDB_PrescalerDp_u0__A1_REG CYREG_B0_UDB15_A1
#define CapSense_ClockGen_UDB_PrescalerDp_u0__D0_D1_REG CYREG_B0_UDB15_D0_D1
#define CapSense_ClockGen_UDB_PrescalerDp_u0__D0_REG CYREG_B0_UDB15_D0
#define CapSense_ClockGen_UDB_PrescalerDp_u0__D1_REG CYREG_B0_UDB15_D1
#define CapSense_ClockGen_UDB_PrescalerDp_u0__DP_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define CapSense_ClockGen_UDB_PrescalerDp_u0__F0_F1_REG CYREG_B0_UDB15_F0_F1
#define CapSense_ClockGen_UDB_PrescalerDp_u0__F0_REG CYREG_B0_UDB15_F0
#define CapSense_ClockGen_UDB_PrescalerDp_u0__F1_REG CYREG_B0_UDB15_F1

/* CapSense_CmodCH0 */
#define CapSense_CmodCH0__0__MASK 0x10u
#define CapSense_CmodCH0__0__PC CYREG_PRT6_PC4
#define CapSense_CmodCH0__0__PORT 6u
#define CapSense_CmodCH0__0__SHIFT 4
#define CapSense_CmodCH0__AG CYREG_PRT6_AG
#define CapSense_CmodCH0__AMUX CYREG_PRT6_AMUX
#define CapSense_CmodCH0__BIE CYREG_PRT6_BIE
#define CapSense_CmodCH0__BIT_MASK CYREG_PRT6_BIT_MASK
#define CapSense_CmodCH0__BYP CYREG_PRT6_BYP
#define CapSense_CmodCH0__Cmod_CH0__MASK 0x10u
#define CapSense_CmodCH0__Cmod_CH0__PC CYREG_PRT6_PC4
#define CapSense_CmodCH0__Cmod_CH0__PORT 6u
#define CapSense_CmodCH0__Cmod_CH0__SHIFT 4
#define CapSense_CmodCH0__CTL CYREG_PRT6_CTL
#define CapSense_CmodCH0__DM0 CYREG_PRT6_DM0
#define CapSense_CmodCH0__DM1 CYREG_PRT6_DM1
#define CapSense_CmodCH0__DM2 CYREG_PRT6_DM2
#define CapSense_CmodCH0__DR CYREG_PRT6_DR
#define CapSense_CmodCH0__INP_DIS CYREG_PRT6_INP_DIS
#define CapSense_CmodCH0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define CapSense_CmodCH0__LCD_EN CYREG_PRT6_LCD_EN
#define CapSense_CmodCH0__MASK 0x10u
#define CapSense_CmodCH0__PORT 6u
#define CapSense_CmodCH0__PRT CYREG_PRT6_PRT
#define CapSense_CmodCH0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define CapSense_CmodCH0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define CapSense_CmodCH0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define CapSense_CmodCH0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define CapSense_CmodCH0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define CapSense_CmodCH0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define CapSense_CmodCH0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define CapSense_CmodCH0__PS CYREG_PRT6_PS
#define CapSense_CmodCH0__SHIFT 4
#define CapSense_CmodCH0__SLW CYREG_PRT6_SLW

/* CapSense_CompCH0_ctComp */
#define CapSense_CompCH0_ctComp__CLK CYREG_CMP1_CLK
#define CapSense_CompCH0_ctComp__CMP_MASK 0x02u
#define CapSense_CompCH0_ctComp__CMP_NUMBER 1u
#define CapSense_CompCH0_ctComp__CR CYREG_CMP1_CR
#define CapSense_CompCH0_ctComp__LUT__CR CYREG_LUT1_CR
#define CapSense_CompCH0_ctComp__LUT__MSK CYREG_LUT_MSK
#define CapSense_CompCH0_ctComp__LUT__MSK_MASK 0x02u
#define CapSense_CompCH0_ctComp__LUT__MSK_SHIFT 1
#define CapSense_CompCH0_ctComp__LUT__MX CYREG_LUT1_MX
#define CapSense_CompCH0_ctComp__LUT__SR CYREG_LUT_SR
#define CapSense_CompCH0_ctComp__LUT__SR_MASK 0x02u
#define CapSense_CompCH0_ctComp__LUT__SR_SHIFT 1
#define CapSense_CompCH0_ctComp__PM_ACT_CFG CYREG_PM_ACT_CFG7
#define CapSense_CompCH0_ctComp__PM_ACT_MSK 0x02u
#define CapSense_CompCH0_ctComp__PM_STBY_CFG CYREG_PM_STBY_CFG7
#define CapSense_CompCH0_ctComp__PM_STBY_MSK 0x02u
#define CapSense_CompCH0_ctComp__SW0 CYREG_CMP1_SW0
#define CapSense_CompCH0_ctComp__SW2 CYREG_CMP1_SW2
#define CapSense_CompCH0_ctComp__SW3 CYREG_CMP1_SW3
#define CapSense_CompCH0_ctComp__SW4 CYREG_CMP1_SW4
#define CapSense_CompCH0_ctComp__SW6 CYREG_CMP1_SW6
#define CapSense_CompCH0_ctComp__TR0 CYREG_CMP1_TR0
#define CapSense_CompCH0_ctComp__TR1 CYREG_CMP1_TR1
#define CapSense_CompCH0_ctComp__TRIM__TR0 CYREG_FLSHID_MFG_CFG_CMP1_TR0
#define CapSense_CompCH0_ctComp__TRIM__TR0_HS CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS
#define CapSense_CompCH0_ctComp__TRIM__TR1 CYREG_FLSHID_MFG_CFG_CMP1_TR1
#define CapSense_CompCH0_ctComp__TRIM__TR1_HS CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS
#define CapSense_CompCH0_ctComp__WRK CYREG_CMP_WRK
#define CapSense_CompCH0_ctComp__WRK_MASK 0x02u
#define CapSense_CompCH0_ctComp__WRK_SHIFT 1

/* CapSense_IdacCH0_viDAC8 */
#define CapSense_IdacCH0_viDAC8__CR0 CYREG_DAC3_CR0
#define CapSense_IdacCH0_viDAC8__CR1 CYREG_DAC3_CR1
#define CapSense_IdacCH0_viDAC8__D CYREG_DAC3_D
#define CapSense_IdacCH0_viDAC8__PM_ACT_CFG CYREG_PM_ACT_CFG8
#define CapSense_IdacCH0_viDAC8__PM_ACT_MSK 0x08u
#define CapSense_IdacCH0_viDAC8__PM_STBY_CFG CYREG_PM_STBY_CFG8
#define CapSense_IdacCH0_viDAC8__PM_STBY_MSK 0x08u
#define CapSense_IdacCH0_viDAC8__STROBE CYREG_DAC3_STROBE
#define CapSense_IdacCH0_viDAC8__SW0 CYREG_DAC3_SW0
#define CapSense_IdacCH0_viDAC8__SW2 CYREG_DAC3_SW2
#define CapSense_IdacCH0_viDAC8__SW3 CYREG_DAC3_SW3
#define CapSense_IdacCH0_viDAC8__SW4 CYREG_DAC3_SW4
#define CapSense_IdacCH0_viDAC8__TR CYREG_DAC3_TR
#define CapSense_IdacCH0_viDAC8__TRIM__M1 CYREG_FLSHID_CUST_TABLES_DAC3_M1
#define CapSense_IdacCH0_viDAC8__TRIM__M2 CYREG_FLSHID_CUST_TABLES_DAC3_M2
#define CapSense_IdacCH0_viDAC8__TRIM__M3 CYREG_FLSHID_CUST_TABLES_DAC3_M3
#define CapSense_IdacCH0_viDAC8__TRIM__M4 CYREG_FLSHID_CUST_TABLES_DAC3_M4
#define CapSense_IdacCH0_viDAC8__TRIM__M5 CYREG_FLSHID_CUST_TABLES_DAC3_M5
#define CapSense_IdacCH0_viDAC8__TRIM__M6 CYREG_FLSHID_CUST_TABLES_DAC3_M6
#define CapSense_IdacCH0_viDAC8__TRIM__M7 CYREG_FLSHID_CUST_TABLES_DAC3_M7
#define CapSense_IdacCH0_viDAC8__TRIM__M8 CYREG_FLSHID_CUST_TABLES_DAC3_M8
#define CapSense_IdacCH0_viDAC8__TST CYREG_DAC3_TST

/* CapSense_IntClock */
#define CapSense_IntClock__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define CapSense_IntClock__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define CapSense_IntClock__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define CapSense_IntClock__CFG2_SRC_SEL_MASK 0x07u
#define CapSense_IntClock__INDEX 0x00u
#define CapSense_IntClock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define CapSense_IntClock__PM_ACT_MSK 0x01u
#define CapSense_IntClock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define CapSense_IntClock__PM_STBY_MSK 0x01u

/* CapSense_IsrCH0 */
#define CapSense_IsrCH0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define CapSense_IsrCH0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define CapSense_IsrCH0__INTC_MASK 0x01u
#define CapSense_IsrCH0__INTC_NUMBER 0u
#define CapSense_IsrCH0__INTC_PRIOR_NUM 7u
#define CapSense_IsrCH0__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define CapSense_IsrCH0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define CapSense_IsrCH0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* CapSense_MeasureCH0 */
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_A0_REG CYREG_B0_UDB13_14_A0
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_A1_REG CYREG_B0_UDB13_14_A1
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_D0_REG CYREG_B0_UDB13_14_D0
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_D1_REG CYREG_B0_UDB13_14_D1
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_F0_REG CYREG_B0_UDB13_14_F0
#define CapSense_MeasureCH0_UDB_Counter_u0__16BIT_F1_REG CYREG_B0_UDB13_14_F1
#define CapSense_MeasureCH0_UDB_Counter_u0__A0_A1_REG CYREG_B0_UDB13_A0_A1
#define CapSense_MeasureCH0_UDB_Counter_u0__A0_REG CYREG_B0_UDB13_A0
#define CapSense_MeasureCH0_UDB_Counter_u0__A1_REG CYREG_B0_UDB13_A1
#define CapSense_MeasureCH0_UDB_Counter_u0__D0_D1_REG CYREG_B0_UDB13_D0_D1
#define CapSense_MeasureCH0_UDB_Counter_u0__D0_REG CYREG_B0_UDB13_D0
#define CapSense_MeasureCH0_UDB_Counter_u0__D1_REG CYREG_B0_UDB13_D1
#define CapSense_MeasureCH0_UDB_Counter_u0__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define CapSense_MeasureCH0_UDB_Counter_u0__F0_F1_REG CYREG_B0_UDB13_F0_F1
#define CapSense_MeasureCH0_UDB_Counter_u0__F0_REG CYREG_B0_UDB13_F0
#define CapSense_MeasureCH0_UDB_Counter_u0__F1_REG CYREG_B0_UDB13_F1
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_A0_REG CYREG_B0_UDB12_13_A0
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_A1_REG CYREG_B0_UDB12_13_A1
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_D0_REG CYREG_B0_UDB12_13_D0
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_D1_REG CYREG_B0_UDB12_13_D1
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_F0_REG CYREG_B0_UDB12_13_F0
#define CapSense_MeasureCH0_UDB_Window_u0__16BIT_F1_REG CYREG_B0_UDB12_13_F1
#define CapSense_MeasureCH0_UDB_Window_u0__A0_A1_REG CYREG_B0_UDB12_A0_A1
#define CapSense_MeasureCH0_UDB_Window_u0__A0_REG CYREG_B0_UDB12_A0
#define CapSense_MeasureCH0_UDB_Window_u0__A1_REG CYREG_B0_UDB12_A1
#define CapSense_MeasureCH0_UDB_Window_u0__D0_D1_REG CYREG_B0_UDB12_D0_D1
#define CapSense_MeasureCH0_UDB_Window_u0__D0_REG CYREG_B0_UDB12_D0
#define CapSense_MeasureCH0_UDB_Window_u0__D1_REG CYREG_B0_UDB12_D1
#define CapSense_MeasureCH0_UDB_Window_u0__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define CapSense_MeasureCH0_UDB_Window_u0__F0_F1_REG CYREG_B0_UDB12_F0_F1
#define CapSense_MeasureCH0_UDB_Window_u0__F0_REG CYREG_B0_UDB12_F0
#define CapSense_MeasureCH0_UDB_Window_u0__F1_REG CYREG_B0_UDB12_F1

/* CapSense_PortCH0 */
#define CapSense_PortCH0__0__MASK 0x40u
#define CapSense_PortCH0__0__PC CYREG_PRT5_PC6
#define CapSense_PortCH0__0__PORT 5u
#define CapSense_PortCH0__0__SHIFT 6
#define CapSense_PortCH0__AG CYREG_PRT5_AG
#define CapSense_PortCH0__AMUX CYREG_PRT5_AMUX
#define CapSense_PortCH0__BIE CYREG_PRT5_BIE
#define CapSense_PortCH0__BIT_MASK CYREG_PRT5_BIT_MASK
#define CapSense_PortCH0__BYP CYREG_PRT5_BYP
#define CapSense_PortCH0__CTL CYREG_PRT5_CTL
#define CapSense_PortCH0__DM0 CYREG_PRT5_DM0
#define CapSense_PortCH0__DM1 CYREG_PRT5_DM1
#define CapSense_PortCH0__DM2 CYREG_PRT5_DM2
#define CapSense_PortCH0__DR CYREG_PRT5_DR
#define CapSense_PortCH0__INP_DIS CYREG_PRT5_INP_DIS
#define CapSense_PortCH0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define CapSense_PortCH0__LCD_EN CYREG_PRT5_LCD_EN
#define CapSense_PortCH0__MASK 0x40u
#define CapSense_PortCH0__PORT 5u
#define CapSense_PortCH0__ProximitySensor0_0__PROX__MASK 0x40u
#define CapSense_PortCH0__ProximitySensor0_0__PROX__PC CYREG_PRT5_PC6
#define CapSense_PortCH0__ProximitySensor0_0__PROX__PORT 5u
#define CapSense_PortCH0__ProximitySensor0_0__PROX__SHIFT 6
#define CapSense_PortCH0__PRT CYREG_PRT5_PRT
#define CapSense_PortCH0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define CapSense_PortCH0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define CapSense_PortCH0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define CapSense_PortCH0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define CapSense_PortCH0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define CapSense_PortCH0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define CapSense_PortCH0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define CapSense_PortCH0__PS CYREG_PRT5_PS
#define CapSense_PortCH0__SHIFT 6
#define CapSense_PortCH0__SLW CYREG_PRT5_SLW

/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 24000000U
#define BCLK__BUS_CLK__KHZ 24000U
#define BCLK__BUS_CLK__MHZ 24U
#define CY_VERSION "PSoC Creator  3.1 SP1"
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 6u
#define CYDEV_CHIP_DIE_PSOC4A 3u
#define CYDEV_CHIP_DIE_PSOC5LP 5u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E123069u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 3u
#define CYDEV_CHIP_MEMBER_4D 2u
#define CYDEV_CHIP_MEMBER_4F 4u
#define CYDEV_CHIP_MEMBER_5A 6u
#define CYDEV_CHIP_MEMBER_5B 5u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00000001u
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDA 5.0
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5.0
#define CYDEV_VDDD_MV 5000
#define CYDEV_VDDIO0 5.0
#define CYDEV_VDDIO0_MV 5000
#define CYDEV_VDDIO1 5.0
#define CYDEV_VDDIO1_MV 5000
#define CYDEV_VDDIO2 5.0
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5.0
#define CYDEV_VDDIO3_MV 5000
#define CYDEV_VIO0 5.0
#define CYDEV_VIO0_MV 5000
#define CYDEV_VIO1 5.0
#define CYDEV_VIO1_MV 5000
#define CYDEV_VIO2 5.0
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 5.0
#define CYDEV_VIO3_MV 5000
#define CYIPBLOCK_ARM_CM3_VERSION 0
#define CYIPBLOCK_P3_ANAIF_VERSION 0
#define CYIPBLOCK_P3_CAN_VERSION 0
#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
#define CYIPBLOCK_P3_COMP_VERSION 0
#define CYIPBLOCK_P3_DECIMATOR_VERSION 0
#define CYIPBLOCK_P3_DFB_VERSION 0
#define CYIPBLOCK_P3_DMA_VERSION 0
#define CYIPBLOCK_P3_DRQ_VERSION 0
#define CYIPBLOCK_P3_DSM_VERSION 0
#define CYIPBLOCK_P3_EMIF_VERSION 0
#define CYIPBLOCK_P3_I2C_VERSION 0
#define CYIPBLOCK_P3_LCD_VERSION 0
#define CYIPBLOCK_P3_LPF_VERSION 0
#define CYIPBLOCK_P3_OPAMP_VERSION 0
#define CYIPBLOCK_P3_PM_VERSION 0
#define CYIPBLOCK_P3_SCCT_VERSION 0
#define CYIPBLOCK_P3_TIMER_VERSION 0
#define CYIPBLOCK_P3_USB_VERSION 0
#define CYIPBLOCK_P3_VIDAC_VERSION 0
#define CYIPBLOCK_P3_VREF_VERSION 0
#define CYIPBLOCK_S8_GPIO_VERSION 0
#define CYIPBLOCK_S8_IRQ_VERSION 0
#define CYIPBLOCK_S8_SAR_VERSION 0
#define CYIPBLOCK_S8_SIO_VERSION 0
#define CYIPBLOCK_S8_UDB_VERSION 0
#define DMA_CHANNELS_USED__MASK0 0x00000000u
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
