# Static Timing Analysis

Project : | capsense_Proximity
Build Time : | 03/29/15 19:07:35
Device : | CY8C5868AXI-LP035
Temperature : | -40C - 85/125C
VDDA : | 5.00
VDDABUF : | 5.00
VDDD : | 5.00
VDDIO0 : | 5.00
VDDIO1 : | 5.00
VDDIO2 : | 5.00
VDDIO3 : | 5.00
VUSB : | 5.00
Voltage : | 5.0

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CapSense_IntClock | CyMASTER_CLK | 12.000 MHz | 12.000 MHz | 38.319 MHz |
CyBUS_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CyPLL_OUT | CyPLL_OUT | 24.000 MHz | 24.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
+ Destination Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
Path Delay Requirement : 83.3333ns(12 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 | 38.319 MHz | 26.097 | 57.236 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_win_1\/main_0 | 4.466
macrocell10 | U(1,5) | 1 | \CapSense:MeasureCH0:cs_addr_win_1\ | \CapSense:MeasureCH0:cs_addr_win_1\/main_0 | \CapSense:MeasureCH0:cs_addr_win_1\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_1\ | \CapSense:MeasureCH0:cs_addr_win_1\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 | 2.901
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 | 38.847 MHz | 25.742 | 57.591 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_win_1\/main_1 | 4.141
macrocell10 | U(1,5) | 1 | \CapSense:MeasureCH0:cs_addr_win_1\ | \CapSense:MeasureCH0:cs_addr_win_1\/main_1 | \CapSense:MeasureCH0:cs_addr_win_1\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_1\ | \CapSense:MeasureCH0:cs_addr_win_1\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 | 2.901
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 40.530 MHz | 24.673 | 58.660 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_win_0\/main_0 | 3.627
macrocell9 | U(0,4) | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/main_0 | \CapSense:MeasureCH0:cs_addr_win_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 2.316
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_2 | 40.588 MHz | 24.638 | 58.695 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_win_2\/main_0 | 3.599
macrocell11 | U(1,4) | 1 | \CapSense:MeasureCH0:cs_addr_win_2\ | \CapSense:MeasureCH0:cs_addr_win_2\/main_0 | \CapSense:MeasureCH0:cs_addr_win_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_2\ | \CapSense:MeasureCH0:cs_addr_win_2\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_2 | 2.309
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 40.642 MHz | 24.605 | 58.728 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 | 3.573
macrocell8 | U(0,4) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 2.302
datapathcell4 | U(0,4) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 | 40.652 MHz | 24.599 | 58.734 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_cnt_1\/main_1 | 3.573
macrocell7 | U(0,4) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_1\ | \CapSense:MeasureCH0:cs_addr_cnt_1\/main_1 | \CapSense:MeasureCH0:cs_addr_cnt_1\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_1\ | \CapSense:MeasureCH0:cs_addr_cnt_1\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 | 2.296
datapathcell4 | U(0,4) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 | 40.659 MHz | 24.595 | 58.738 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | 3.850
Route |  | 1 | \CapSense:MeasureCH0:zw0\ | \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb | \CapSense:MeasureCH0:cs_addr_cnt_0\/main_1 | 3.573
macrocell6 | U(0,4) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_0\ | \CapSense:MeasureCH0:cs_addr_cnt_0\/main_1 | \CapSense:MeasureCH0:cs_addr_cnt_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_0\ | \CapSense:MeasureCH0:cs_addr_cnt_0\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 | 2.292
datapathcell4 | U(0,4) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 41.166 MHz | 24.292 | 59.041 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_win_0\/main_1 | 3.276
macrocell9 | U(0,4) | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/main_1 | \CapSense:MeasureCH0:cs_addr_win_0\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_0\ | \CapSense:MeasureCH0:cs_addr_win_0\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 | 2.316
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_2 | 41.191 MHz | 24.277 | 59.056 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_win_2\/main_1 | 3.268
macrocell11 | U(1,4) | 1 | \CapSense:MeasureCH0:cs_addr_win_2\ | \CapSense:MeasureCH0:cs_addr_win_2\/main_1 | \CapSense:MeasureCH0:cs_addr_win_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_win_2\ | \CapSense:MeasureCH0:cs_addr_win_2\/q | \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_2 | 2.309
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 41.237 MHz | 24.250 | 59.083 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell5 | U(1,4) | 1 | \CapSense:MeasureCH0:UDB:Window:u0\ | \CapSense:MeasureCH0:UDB:Window:u0\/clock | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | 3.820
Route |  | 1 | \CapSense:MeasureCH0:zw1\ | \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_2 | 3.248
macrocell8 | U(0,4) | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/main_2 | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | 3.350
Route |  | 1 | \CapSense:MeasureCH0:cs_addr_cnt_2\ | \CapSense:MeasureCH0:cs_addr_cnt_2\/q | \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 | 2.302
datapathcell4 | U(0,4) | 1 | \CapSense:MeasureCH0:UDB:Counter:u0\ |  | SETUP | 11.530
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : CapSense_IntClock : Positive edge
+ Destination Clock : CapSense_IntClock : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\CapSense:ClockGen:sC16:PRSdp:u1\/cmsbo | \CapSense:ClockGen:sC16:PRSdp:u0\/cmsbi | 2.250 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell3 | U(1,3) | 1 | \CapSense:ClockGen:sC16:PRSdp:u1\ | \CapSense:ClockGen:sC16:PRSdp:u1\/clock | \CapSense:ClockGen:sC16:PRSdp:u1\/cmsbo | 2.250
Route |  | 1 | \CapSense:ClockGen:sC16:PRSdp:u1.cmsbo__sig\ | \CapSense:ClockGen:sC16:PRSdp:u1\/cmsbo | \CapSense:ClockGen:sC16:PRSdp:u0\/cmsbi | 0.000
datapathcell2 | U(0,3) | 1 | \CapSense:ClockGen:sC16:PRSdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:tmp_ppulse_reg\/q | \CapSense:ClockGen:tmp_ppulse_dly\/main_0 | 3.533 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell5 | U(1,5) | 1 | \CapSense:ClockGen:tmp_ppulse_reg\ | \CapSense:ClockGen:tmp_ppulse_reg\/clock_0 | \CapSense:ClockGen:tmp_ppulse_reg\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:tmp_ppulse_reg\ | \CapSense:ClockGen:tmp_ppulse_reg\/q | \CapSense:ClockGen:tmp_ppulse_dly\/main_0 | 2.283
macrocell4 | U(1,5) | 1 | \CapSense:ClockGen:tmp_ppulse_dly\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:Net_1603\/q | \CapSense:MeasureCH0:wndState_1\/main_7 | 3.556 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell15 | U(0,3) | 1 | \CapSense:Net_1603\ | \CapSense:Net_1603\/clock_0 | \CapSense:Net_1603\/q | 1.250
Route |  | 1 | \CapSense:Net_1603\ | \CapSense:Net_1603\/q | \CapSense:MeasureCH0:wndState_1\/main_7 | 2.306
macrocell13 | U(0,3) | 1 | \CapSense:MeasureCH0:wndState_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:Net_1603\/q | \CapSense:Net_1603\/main_6 | 3.556 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell15 | U(0,3) | 1 | \CapSense:Net_1603\ | \CapSense:Net_1603\/clock_0 | \CapSense:Net_1603\/q | 1.250
macrocell15 | U(0,3) | 1 | \CapSense:Net_1603\ | \CapSense:Net_1603\/q | \CapSense:Net_1603\/main_6 | 2.306
macrocell15 | U(0,3) | 1 | \CapSense:Net_1603\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:clock_detect_reg\/q | \CapSense:ClockGen:sC16:PRSdp:u1\/cs_addr_0 | 3.559 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell1 | U(1,3) | 1 | \CapSense:ClockGen:clock_detect_reg\ | \CapSense:ClockGen:clock_detect_reg\/clock_0 | \CapSense:ClockGen:clock_detect_reg\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:clock_detect_reg\ | \CapSense:ClockGen:clock_detect_reg\/q | \CapSense:ClockGen:sC16:PRSdp:u1\/cs_addr_0 | 2.309
datapathcell3 | U(1,3) | 1 | \CapSense:ClockGen:sC16:PRSdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:clock_detect_reg\/q | \CapSense:ClockGen:sC16:PRSdp:u0\/cs_addr_0 | 3.571 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell1 | U(1,3) | 1 | \CapSense:ClockGen:clock_detect_reg\ | \CapSense:ClockGen:clock_detect_reg\/clock_0 | \CapSense:ClockGen:clock_detect_reg\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:clock_detect_reg\ | \CapSense:ClockGen:clock_detect_reg\/q | \CapSense:ClockGen:sC16:PRSdp:u0\/cs_addr_0 | 2.321
datapathcell2 | U(0,3) | 1 | \CapSense:ClockGen:sC16:PRSdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:sC16:PRSdp:u0\/sol_msb | \CapSense:ClockGen:sC16:PRSdp:u1\/sir | 3.780 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,3) | 1 | \CapSense:ClockGen:sC16:PRSdp:u0\ | \CapSense:ClockGen:sC16:PRSdp:u0\/clock | \CapSense:ClockGen:sC16:PRSdp:u0\/sol_msb | 3.780
Route |  | 1 | \CapSense:ClockGen:sC16:PRSdp:u0.sol_msb__sig\ | \CapSense:ClockGen:sC16:PRSdp:u0\/sol_msb | \CapSense:ClockGen:sC16:PRSdp:u1\/sir | 0.000
datapathcell3 | U(1,3) | 1 | \CapSense:ClockGen:sC16:PRSdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:cstate_2\/q | \CapSense:ClockGen:cstate_2\/main_4 | 3.849 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(0,3) | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/clock_0 | \CapSense:ClockGen:cstate_2\/q | 1.250
macrocell2 | U(0,3) | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/q | \CapSense:ClockGen:cstate_2\/main_4 | 2.599
macrocell2 | U(0,3) | 1 | \CapSense:ClockGen:cstate_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:cstate_2\/q | \CapSense:ClockGen:inter_reset\/main_3 | 3.849 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(0,3) | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/clock_0 | \CapSense:ClockGen:cstate_2\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/q | \CapSense:ClockGen:inter_reset\/main_3 | 2.599
macrocell3 | U(0,3) | 1 | \CapSense:ClockGen:inter_reset\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

\CapSense:ClockGen:cstate_2\/q | \CapSense:mrst\/main_3 | 3.849 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(0,3) | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/clock_0 | \CapSense:ClockGen:cstate_2\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:cstate_2\ | \CapSense:ClockGen:cstate_2\/q | \CapSense:mrst\/main_3 | 2.599
macrocell17 | U(0,3) | 1 | \CapSense:mrst\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Asynchronous Constraints
+ Recovery
+ Source Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
+ Destination Clock : CapSense_IntClock : Positive edge(Required Frequency 12 MHz)
Path Delay Requirement : 83.3333ns(12 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 215.703 MHz | 4.636 | 78.697 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,3) | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/clock_0 | \CapSense:ClockGen:inter_reset\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 3.386
count7cell | U(1,3) | 1 | \CapSense:ClockGen:ScanSpeed\ |  | RECOVERY | -0.000
Clock |  |  |  |  | Skew | 0.000

+ Removal
+ Source Clock : CapSense_IntClock : Positive edge
+ Destination Clock : CapSense_IntClock : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 4.636 |

Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(0,3) | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/clock_0 | \CapSense:ClockGen:inter_reset\/q | 1.250
Route |  | 1 | \CapSense:ClockGen:inter_reset\ | \CapSense:ClockGen:inter_reset\/q | \CapSense:ClockGen:ScanSpeed\/reset | 3.386
count7cell | U(1,3) | 1 | \CapSense:ClockGen:ScanSpeed\ |  | REMOVAL | 0.000
Clock |  |  |  |  | Skew | 0.000