Static Timing Analysis

Project : Design01
Build Time : 05/11/15 07:12:57
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_2_theACLK(fixed-function) ADC_SAR_2_theACLK(fixed-function) 1.091 MHz 1.091 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_SAR_2_theACLK CyMASTER_CLK 1.091 MHz 1.091 MHz N/A
LCD_SegStatic_1_InClock CyMASTER_CLK 60.000  Hz 60.000  Hz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
LCD_SegStatic_1_InClock(routed) LCD_SegStatic_1_InClock(routed) 60.000  Hz 60.000  Hz N/A