Static Timing Analysis

Project : ADC_SAR_DMA_12Bit_Continuous
Build Time : 04/06/20 00:15:29
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 135.538 MHz
ADC_SAR_theACLK CyMASTER_CLK 1.091 MHz 1.091 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\USBUART:nrqSync:genblk1[5]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 135.538 MHz 7.378 34.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[5]:INST\ \USBUART:nrqSync:genblk1[5]:INST\/clock \USBUART:nrqSync:genblk1[5]:INST\/out 1.020
Route 1 \USBUART:Net_2040_5\ \USBUART:nrqSync:genblk1[5]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 5.858
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 187.161 MHz 5.343 36.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/clock \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt 2.550
Route 1 \USBUART:EPs_1_to_7_dma_complete\ \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.293
statusicell2 U(1,4) 1 \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[3]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 224.719 MHz 4.450 37.217
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[3]:INST\ \USBUART:nrqSync:genblk1[3]:INST\/clock \USBUART:nrqSync:genblk1[3]:INST\/out 1.020
Route 1 \USBUART:Net_2040_3\ \USBUART:nrqSync:genblk1[3]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 2.930
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[6]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 224.820 MHz 4.448 37.219
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[6]:INST\ \USBUART:nrqSync:genblk1[6]:INST\/clock \USBUART:nrqSync:genblk1[6]:INST\/out 1.020
Route 1 \USBUART:Net_2040_6\ \USBUART:nrqSync:genblk1[6]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 2.928
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[7]:INST\/out \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 225.124 MHz 4.442 37.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[7]:INST\ \USBUART:nrqSync:genblk1[7]:INST\/clock \USBUART:nrqSync:genblk1[7]:INST\/out 1.020
Route 1 \USBUART:Net_2040_7\ \USBUART:nrqSync:genblk1[7]:INST\/out \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.922
statusicell2 U(1,4) 1 \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[1]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 225.378 MHz 4.437 37.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[1]:INST\ \USBUART:nrqSync:genblk1[1]:INST\/clock \USBUART:nrqSync:genblk1[1]:INST\/out 1.020
Route 1 \USBUART:Net_2040_1\ \USBUART:nrqSync:genblk1[1]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.917
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[2]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 225.428 MHz 4.436 37.231
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[2]:INST\ \USBUART:nrqSync:genblk1[2]:INST\/clock \USBUART:nrqSync:genblk1[2]:INST\/out 1.020
Route 1 \USBUART:Net_2040_2\ \USBUART:nrqSync:genblk1[2]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 2.916
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[0]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 225.632 MHz 4.432 37.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[0]:INST\ \USBUART:nrqSync:genblk1[0]:INST\/clock \USBUART:nrqSync:genblk1[0]:INST\/out 1.020
Route 1 \USBUART:Net_2040_0\ \USBUART:nrqSync:genblk1[0]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.912
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USBUART:nrqSync:genblk1[4]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 225.785 MHz 4.429 37.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[4]:INST\ \USBUART:nrqSync:genblk1[4]:INST\/clock \USBUART:nrqSync:genblk1[4]:INST\/out 1.020
Route 1 \USBUART:Net_2040_4\ \USBUART:nrqSync:genblk1[4]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 2.909
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\USBUART:nrqSync:genblk1[4]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 1.259
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[4]:INST\ \USBUART:nrqSync:genblk1[4]:INST\/clock \USBUART:nrqSync:genblk1[4]:INST\/out 0.350
Route 1 \USBUART:Net_2040_4\ \USBUART:nrqSync:genblk1[4]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 2.909
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[0]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 1.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[0]:INST\ \USBUART:nrqSync:genblk1[0]:INST\/clock \USBUART:nrqSync:genblk1[0]:INST\/out 0.350
Route 1 \USBUART:Net_2040_0\ \USBUART:nrqSync:genblk1[0]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.912
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[2]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 1.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[2]:INST\ \USBUART:nrqSync:genblk1[2]:INST\/clock \USBUART:nrqSync:genblk1[2]:INST\/out 0.350
Route 1 \USBUART:Net_2040_2\ \USBUART:nrqSync:genblk1[2]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 2.916
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[1]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 1.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USBUART:nrqSync:genblk1[1]:INST\ \USBUART:nrqSync:genblk1[1]:INST\/clock \USBUART:nrqSync:genblk1[1]:INST\/out 0.350
Route 1 \USBUART:Net_2040_1\ \USBUART:nrqSync:genblk1[1]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.917
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[7]:INST\/out \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 1.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[7]:INST\ \USBUART:nrqSync:genblk1[7]:INST\/clock \USBUART:nrqSync:genblk1[7]:INST\/out 0.350
Route 1 \USBUART:Net_2040_7\ \USBUART:nrqSync:genblk1[7]:INST\/out \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.922
statusicell2 U(1,4) 1 \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[6]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 1.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[6]:INST\ \USBUART:nrqSync:genblk1[6]:INST\/clock \USBUART:nrqSync:genblk1[6]:INST\/out 0.350
Route 1 \USBUART:Net_2040_6\ \USBUART:nrqSync:genblk1[6]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 2.928
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[3]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 1.280
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[3]:INST\ \USBUART:nrqSync:genblk1[3]:INST\/clock \USBUART:nrqSync:genblk1[3]:INST\/out 0.350
Route 1 \USBUART:Net_2040_3\ \USBUART:nrqSync:genblk1[3]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 2.930
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/clock \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt 2.550
Route 1 \USBUART:EPs_1_to_7_dma_complete\ \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.293
statusicell2 U(1,4) 1 \USBUART:EP8_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USBUART:nrqSync:genblk1[5]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 4.208
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USBUART:nrqSync:genblk1[5]:INST\ \USBUART:nrqSync:genblk1[5]:INST\/clock \USBUART:nrqSync:genblk1[5]:INST\/out 0.350
Route 1 \USBUART:Net_2040_5\ \USBUART:nrqSync:genblk1[5]:INST\/out \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 5.858
statusicell1 U(0,4) 1 \USBUART:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000