LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY top_tb IS
END top_tb;
 
ARCHITECTURE behavior OF top_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DTMF_AC97_top
    PORT(
         clk_i : IN  std_logic;
         rstn_i : IN  std_logic;
         AC97_clk_i : IN  std_logic;
         AC97_resetn_o : OUT  std_logic;
         AC97_Sync_o : OUT  std_logic;
         AC97_SData_o : OUT  std_logic;
         AC97_SData_i : IN  std_logic;
         LED_o : OUT  std_logic_vector(3 downto 0);
         RXD_i : IN  std_logic;
         TXD_o : OUT  std_logic
        );
    END COMPONENT;
	  
	  
	 COMPONENT ac97_model is
	  generic (
		 BIT_CLK_STARTUP_TIME : time := 100 ns
		 );
	  port (
		 AC97Reset_n : in std_logic;
		 Bit_Clk   : out  std_logic;
		 Sync      : in std_logic;
		 SData_Out : in std_logic;
		 SData_In  : out  std_logic
		 );
	end COMPONENT;  

   --Inputs
   signal clk_i : std_logic := '0';
   signal rstn_i : std_logic := '0';
   signal AC97_clk_i : std_logic := '0';
   signal AC97_SData_i : std_logic := '0';
   signal RXD_i : std_logic := '0';

 	--Outputs
   signal AC97_resetn_o : std_logic;
   signal AC97_Sync_o : std_logic;
   signal AC97_SData_o : std_logic;
   signal LED_o : std_logic_vector(3 downto 0);
   signal TXD_o : std_logic;

   -- Clock period definitions
   constant clk_i_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DTMF_AC97_top PORT MAP (
          clk_i => clk_i,
          rstn_i => rstn_i,
          AC97_clk_i => AC97_clk_i,
          AC97_resetn_o => AC97_resetn_o,
          AC97_Sync_o => AC97_Sync_o,
          AC97_SData_o => AC97_SData_o,
          AC97_SData_i => AC97_SData_i,
          LED_o => LED_o,
          RXD_i => RXD_i,
          TXD_o => TXD_o
        );
kodek_model: ac97_model
  port map (
    AC97Reset_n => AC97_resetn_o,
    Bit_Clk    => AC97_clk_i,
    Sync       => AC97_Sync_o,
    SData_Out  => AC97_SData_o,
    SData_In   => AC97_SData_i
    );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
		rstn_i <= '0';
      wait for 100 ns;	
		rstn_i <= '1';
      wait for clk_i_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;