Page 1 .\ADDS_21161_EzKit_.asm ADI ADSP-211xx Family Elf Assembler (2.4.5.4) 12 Nov 2005 12:54:35 offset opcode line ====== ====== ==== 1 #include 2 3 #include 4 #include 5 6 0 7 .segment /dm seg_dmda; 8 9 /* AD1836 stereo-channel data holders - used for DSP processing of audio data received from codec */ 10 // input channels 11 .var _Left_Channel_In0; /* Input values from the 2 AD1836 internal stereo ADCs */ 12 .var _Left_Channel_In1; /* 1/8th inch stereo jack connected to internal stereo ADC1 */ 13 .var _Right_Channel_In0; 14 .var _Right_Channel_In1; 15 .var _Left_Channel_SPDIF_rx; /* Input values from the DAR CS8414 */ 16 .var _Right_Channel_SPDIF_rx; 17 //output channels 18 .var _Left_Channel_Out0; /* Output values for the 3 AD1836 internal stereo DACs */ 19 .var _Left_Channel_Out1; /* Left and Right Channel 0 DACs go to headphone jack */ 20 .var _Left_Channel_Out2; 21 .var _Right_Channel_Out0; 22 .var _Right_Channel_Out1; 23 .var _Right_Channel_Out2; 24 .var _Left_Channel_AD1852; /* Output values for AD1852 stereo DAC */ 25 .var _Right_Channel_AD1852; 26 27 .var _Left_Channel; /* Can use these variables as intermediate results to next filtering stage */ 28 .var _Right_Channel; 29 30 .global _Left_Channel_In0; 31 .global _Left_Channel_In1; 32 .global _Right_Channel_In0; 33 .global _Right_Channel_In1; 34 .global _Left_Channel_Out0; 35 .global _Left_Channel_Out1; 36 .global _Left_Channel_Out2; 37 .global _Right_Channel_Out0; 38 .global _Right_Channel_Out1; 39 .global _Right_Channel_Out2; 40 .global _Left_Channel_AD1852; 41 .global _Right_Channel_AD1852; 42 .global _Left_Channel_SPDIF_rx; 43 .global _Right_Channel_SPDIF_rx; 44 45 .extern _rx0a_buf; 46 .extern _tx2a_buf; 47 .extern _i; 48 .extern _DelayLine; // bufor probek 49 50 .endseg; 51 52 0 53 .segment /pm seg_pmco; 54 //############################################################# 55 //####### procedura odczytująca próbki z wejścia AUDIO ######## 56 //############################################################# 57 0 58 _Receive_Samples: 59 .global _Receive_Samples; /* get AD1836 left channel input samples, save to data holders for processing */ 0 0f01ffffffe1 60 r1 = -31; 1 100000000000 61 r0 = dm(_rx0a_buf + Internal_ADC_L0); 2 013e000da001 62 f0 = float r0 by r1; 3 110000000000 63 dm(_Left_Channel_In0) = f0; 4 100000000000 64 r0 = dm(_rx0a_buf + Internal_ADC_L1); f0 = float r0 by r1; dm(_Left_Channel_In1) = f0; 5 013e000da001 64 6 110000000000 64 65 //dm(_Right_Channel_In1) = r0; 66 //R0 = ABS R0; 7 100000000000 67 r0 = dm(_rx0a_buf + AUX_ADC_L0); f0 = float r0 by r1; dm(_Left_Channel_SPDIF_rx) = r0; 8 013e000da001 67 9 110000000000 67 68 69 /* get AD1836 right channel input samples, save to data holders for processing */ a 100000000000 70 r0 = dm(_rx0a_buf + Internal_ADC_R0); f0 = float r0 by r1; dm(_Right_Channel_In0) = f0; b 013e000da001 70 c 110000000000 70 d 100000000000 71 r0 = dm(_rx0a_buf + Internal_ADC_R1); f0 = float r0 by r1; dm(_Right_Channel_In1) = f0; e 013e000da001 71 f 110000000000 71 10 100000000000 72 r0 = dm(_rx0a_buf + AUX_ADC_R0); f0 = float r0 by r1; dm(_Right_Channel_SPDIF_rx) = r0; 11 013e000da001 72 12 110000000000 72 73 13 4dfe0e000000 74 leaf_exit; 14 083f34000000 74 15 000000000000 74 16 190000000000 74 17 75 _Receive_Samples.end: 76 77 //############################################################## 78 //####### procedura zapisaująca próbki na wyjścia AUDIO ######## 79 //############################################################## 17 80 _Transmit_Samples: 81 .global _Transmit_Samples; 82 17 0f010000001f 83 r1 = 31; 84 85 /* output processed left ch audio samples to AD1836 */ 18 100000000000 86 f0 = dm(_Left_Channel_Out0); r0 = trunc f0 by r1; dm(_tx2a_buf + Internal_DAC_L0) = r0; 19 013e000dd001 86 1a 110000000000 86 1b 100000000000 87 r0 = dm(_Left_Channel_Out1); r0 = trunc f0 by r1; dm(_tx2a_buf + Internal_DAC_L1) = r0; 1c 013e000dd001 87 1d 110000000000 87 1e 100000000000 88 r0 = dm(_Left_Channel_Out2); r0 = trunc f0 by r1; dm(_tx2a_buf + Internal_DAC_L2) = r0; 1f 013e000dd001 88 20 110000000000 88 21 100000000000 89 r0 = dm(_Left_Channel_AD1852); r0 = trunc f0 by r1; dm(_tx2a_buf + AUX_DAC_L0) = r0; 22 013e000dd001 89 23 110000000000 89 90 91 /* output processed right ch audio samples to AD1836 */ 24 100000000000 92 f0 = dm(_Right_Channel_Out0); r0 = trunc f0 by r1; dm(_tx2a_buf + Internal_DAC_R0) = r0; 25 013e000dd001 92 26 110000000000 92 27 100000000000 93 r0 = dm(_Right_Channel_Out1); r0 = trunc f0 by r1; dm(_tx2a_buf + Internal_DAC_R1) = r0; 28 013e000dd001 93 29 110000000000 93 2a 100000000000 94 r0 = dm(_Right_Channel_Out2); r0 = trunc f0 by r1; dm(_tx2a_buf + Internal_DAC_R2) = r0; 2b 013e000dd001 94 2c 110000000000 94 2d 100000000000 95 r0 = dm(_Right_Channel_AD1852); r0 = trunc f0 by r1; dm(_tx2a_buf + AUX_DAC_R0) = r0; 2e 013e000dd001 95 2f 110000000000 95 96 30 4dfe0e000000 97 leaf_exit; 31 083f34000000 97 32 000000000000 97 33 190000000000 97 34 98 _Transmit_Samples.end: 99 100 //################################################################### 101 //################ procedura przetwarzania dźwięku ################## 102 //################################################################### 103 34 104 _echo_ASM: 105 .global _echo_ASM; 106 34 1402000004fc 107 BIT SET MODE1 SRD1L | SRD1H | SRD2L |SRD2H | SRRFL | SRRFH | SRCU ; 108 // Activate alternate registers 35 000000000000 109 NOP; // Wait for access to alternates 110 36 100000000000 111 f0=dm(_Left_Channel_In1); //zapisanie próbki z mikrofonu do bufora kołowego 37 503e80000000 112 dm(i0,m0)=f0; 113 38 527e00800000 114 f1=dm(i1,m1); //opóznienie 39 54be01000000 115 f2=dm(i2,m2); 116 3a 0f053f333333 117 f5=0.7; 3b 013e00130015 118 f0=f1*f5; 3c 0f053e99999a 119 f5=0.3; 3d 013e00130625 120 f6=f2*f5; 3e 013e00081006 121 f0=f0+f6; 3f 110000000000 122 dm(_Right_Channel_Out0)=f0; //prawy kanał 40 110000000000 123 dm(_Left_Channel_Out0)=f0; //lewy kanał 124 125 41 1422000004fc 126 BIT CLR MODE1 SRD1L | SRD1H | SRD2L |SRD2H | SRRFL | SRRFH | SRCU ; // przywróć podstawowy zestaw rejestrów 42 000000000000 127 NOP; // Wait for access to alternates 128 43 4dfe0e000000 129 leaf_exit; 44 083f34000000 129 45 000000000000 129 46 190000000000 129 47 130 _echo_ASM.end: 131 47 132 _init_echo_ASM: 133 .global _init_echo_ASM; 134 47 1402000004fc 135 BIT SET MODE1 SRD1L | SRD1H | SRD2L |SRD2H | SRRFL | SRRFH | SRCU ; 136 // Activate alternate registers 48 000000000000 137 NOP; // Wait for access to alternates 138 49 0f0000200000 139 r0=0x200000; // bufor probek 4a 703e20000000 140 B0=r0; 4b 743e20800000 141 B1=B0; 4c 743e21000000 142 B2=B0; 143 4d 0f0000013880 144 r0=80000; //długość bufora 4e 703e18000000 145 L0=r0; 4f 703e18800000 146 L1=r0; 50 703e19000000 147 L2=r0; 148 51 0f2000000001 149 M0=1; 52 723e10800000 150 M1=M0; 53 0f2200000001 151 M2=1; 152 54 743e08000000 153 I0=B0; 55 743e00800000 154 R1=B0; 155 56 0f0000009c40 156 R0=40000; //opóźnienie 40 tys. próbek = ok. 1 sekundy 57 013e00001010 157 R0=R1+R0; 58 703e08800000 158 I1=R0; 159 59 0f0000000001 160 R0=1; //opóźnienie 79999 próbek = ok. 2 sekundy 5a 013e00001010 161 R0=R1+R0; 5b 703e09000000 162 I2=R0; 163 5c 1422000004fc 164 BIT CLR MODE1 SRD1L | SRD1H | SRD2L |SRD2H | SRRFL | SRRFH | SRCU ; // przywróć podstawowy zestaw rejestrów 5d 000000000000 165 NOP; // Wait for access to alternates 166 5e 4dfe0e000000 167 leaf_exit; 5f 083f34000000 167 60 000000000000 167 61 190000000000 167 62 168 _init_echo_ASM.end: 169 170 171 .endseg;