/************************************************************************ * * def21161.h * * (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved. * $Revision: 1.7 $ ************************************************************************/ /* ---------------------------------------------------------------------------- def21161.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21161 Last Modification on: $Date: 2004/07/29 11:05:18 $ This include file contains a list of macro "defines" to enable the programmer to use symbolic names for the following ADSP-21161 facilities: - instruction condition codes - system register bit definitions - IOP register address memory map - *most* IOP control/status register bit definitions Changes from def21160 include new I/O flags, SDRAM and SPI interfaces, changes to SPORT, Link Port, and DMA. * 2/12/01 J.T. - fixed WAIT Register Bitfields for ROM Boot waitstates and waitmode - removed IMGR bit 29 in SYSCON, since no mesh processing on 21161 - removed L1DMA2D and L2DMA2D bits in LCTL since no 2-D DMA - removed 2DDMA references to older SPORT/Link DMA parameter register naming conventions - moved DMASTAT reg out of DMA parameters section to general IOP reg section - moved Link Port and SPORT Registers to general IOP section - added defs under IOP register bitfields section for MODE2_SHDW (0x11) - fixed comments for LDCPR bit in SYSCON to indicate DMA chs 8 & 9 - rearranged SYSTAT bitfield definitions to correct order - added LSRQ, DMAC10, DMAC11, DMAC12, DMAC13, DMASTAT, bitfield definitions - fixed SPICTL bitfield hex assignments (per G.L.) for bits 24 to 31 - added bitfield descriptions for IOFLAG, SPICTL, SPISTAT and LCTL IOP registers - removed LARB0, LARB1 bits and added A0LB, L1LB bits in LCTL as shown in 21160/21161 HW reference manuals and for 2106x code compatibility - added SPCTL0/1/2/3 register bitfield definitions for I2S, DSP serial and multichannel modes - fixed which STKYx/y bits pertain only to STKYx register - added G.L.'s alternate SPI DMA parameter register naming conventions - added IOP register name descriptions in comments field for all SPI and SPORT registers - added SP02MCTL and SP13MCTL bitfield descriptions - added additional SPORT bitfied definitions from G.L. * 2/13/01 - JT - changed RBWx bits in WAIT to RBWMx to reflect 21065L compatibility - changed WAIT register bits for def21160.H compatibility - added generic WAIT register bits consistant with HW ref manual - added new WAIT register bitfields for all waitstates and waitmodes combos - fixed comment fields for SPORTx multichannel select registers - more detailed comment fields for SDCTL register * 2/15/01 - JT - fixed 'tRCD' comment under SDRAM bitfield description for tRAS * 2/21/01 - TK - fixed definition of EBxAM entries - fixed definition of EBxWSx entries * 2/22/01 - JT - added alternate LAB0 and LAB1 definitions in LCTL * 2/23/01 - JT - renamed SDCTL bitfield SDCKRx2 to SDCKR_DIV2 * 03/05/01 - TK - fixed example * 03/09/01 - JT - fixed SDTRCD comments in SDCTL from "CAS-to-RAS" to "RAS-to-CAS" delay * 04/02/01 - JT - renamed (alternale link port) SPI DMA count definitions to CSRX and CSTX * 04/03/01 - GL - fixed boot wait state definations so that RBWS0 and RBWS1 refer to the actual bit positions and RBWS0:RBWS7 are changed to RBWST0:RBWST7 so that they don't confict with the bit position definitions * 05/14/01 - JT - In WAIT register, changed "RBWM" bits to "RMAM" to confirm with defs for banks 0 to 3 * 07/04/01 - TK - fixed SENDN bit entry for SPCTLx registers * 08/13/02 - BM - fixed order of LSRQ register. changed bit naming convention so that each bit is only defined once. i.e. 0x00000001 -> BIT_0 etc. Added definitions for multichannel configuration. * 05/06/03 - BM - fixed incorrect bit in SPICTL - Bit 19 SMLS -> NSMLS Here are some example uses: bit set mode1 BR0|IRPTEN|ALUSAT; ustat1=BSO|HPM01|HMSWF; DM(SYSCON)=ustat1; ----------------------------------------------------------------------------- */ /*------------------------------------------------------------------*/ /* ADSP-21161 definitions */ #ifndef __DEF21161_H_ #define __DEF21161_H_ #define BIT_0 0x00000001 #define BIT_1 0x00000002 #define BIT_2 0x00000004 #define BIT_3 0x00000008 #define BIT_4 0x00000010 #define BIT_5 0x00000020 #define BIT_6 0x00000040 #define BIT_7 0x00000080 #define BIT_8 0x00000100 #define BIT_9 0x00000200 #define BIT_10 0x00000400 #define BIT_11 0x00000800 #define BIT_12 0x00001000 #define BIT_13 0x00002000 #define BIT_14 0x00004000 #define BIT_15 0x00008000 #define BIT_16 0x00010000 #define BIT_17 0x00020000 #define BIT_18 0x00040000 #define BIT_19 0x00080000 #define BIT_20 0x00100000 #define BIT_21 0x00200000 #define BIT_22 0x00400000 #define BIT_23 0x00800000 #define BIT_24 0x01000000 #define BIT_25 0x02000000 #define BIT_26 0x04000000 #define BIT_27 0x08000000 #define BIT_28 0x10000000 #define BIT_29 0x20000000 #define BIT_30 0x40000000 #define BIT_31 0x80000000 /*------------------------------------------------------------------------------*/ /* */ /* I/O Processor Register Address Memory Map */ /* */ /*------------------------------------------------------------------------------*/ #define SYSCON 0x00 /* System configuration register */ #define VIRPT 0x01 /* Vector interrupt register */ #define WAIT 0x02 /* External Port Wait register - renamed to EPCON */ #define EPCON 0x02 /* External Port configuration register */ #define SYSTAT 0x03 /* System status register */ /* the upper 32-bits of the 64-bit epbxs are only accessible as 64-bit reference*/ #define EPB0 0x04 /* External port DMA buffer 0 */ #define EPB1 0x06 /* External port DMA buffer 1 */ #define MSGR0 0x08 /* Message register 0 */ #define MSGR1 0x09 /* Message register 1 */ #define MSGR2 0x0a /* Message register 2 */ #define MSGR3 0x0b /* Message register 3 */ #define MSGR4 0x0c /* Message register 4 */ #define MSGR5 0x0d /* Message register 5 */ #define MSGR6 0x0e /* Message register 6 */ #define MSGR7 0x0f /* Message register 7 */ /* IOP shadow registers of the core control regs */ #define PC_SHDW 0x10 /* PC IOP shadow register (PC[23-0]) */ #define MODE2_SHDW 0x11 /* Mode2 IOP shadow register (MODE2[31-25]) */ #define EPB2 0x14 /* External port DMA buffer 2 */ #define EPB3 0x16 /* External port DMA buffer 3 */ #define BMAX 0x18 /* Bus time-out maximum */ #define BCNT 0x19 /* Bus time-out counter */ #define DMAC10 0x1c /* EP DMA10 control register */ #define DMAC11 0x1d /* EP DMA11 control register */ #define DMAC12 0x1e /* EP DMA12 control register */ #define DMAC13 0x1f /* EP DMA13 control register */ #define DMASTAT 0x37 /* DMA channel status register */ /* SPI Registers IOP Register Addresses*/ #define SPICTL 0xb4 /* Serial peripheral-compatible interface control register */ #define SPISTAT 0xb5 /* Serial periipheral-compatible interface status register */ #define SPIRX 0xb7 /* SPI receive data buffer */ #define SPITX 0xb6 /* SPI transmit data buffer */ /* IOFLAG Register Address */ #define IOFLAG 0x1b /* Address of programmable I/O flags 4-11 */ /* IOP registers for SDRAM controller. */ #define SDCTL 0xb8 /* SDRAM control reg. */ #define SDRDIV 0xb9 /* Refresh counter div reg. */ /* Link Port Registers */ #define LBUF0 0xc0 /* Link buffer 0 */ #define LBUF1 0xc2 /* Link buffer 1 */ #define LCTL 0xcc /* Link buffer control */ #define LSRQ 0xd0 /* Link service request and mask registers */ /* SPORT0 */ #define SPCTL0 0x1c0 /* SPORT0 serial port control register */ #define TX0A 0x1c1 /* SPORT0 serial port control register */ #define TX0B 0x1c2 /* SPORT0 transmit secondary B channel data buffer */ #define RX0A 0x1c3 /* SPORT0 receive primary A channel data buffer */ #define RX0B 0x1c4 /* SPORT0 receive secondary B channel data buffer */ #define DIV0 0x1c5 /* SPORT0 divisor for transmit/receive SLCK0 and FS0 */ #define CNT0 0x1c6 /* SPORT0 count register */ /* SPORT2 */ #define SPCTL2 0x1d0 /* SPORT2 serial port control register */ #define TX2A 0x1d1 /* SPORT2 serial port control register */ #define TX2B 0x1d2 /* SPORT2 transmit secondary B channel data buffer */ #define RX2A 0x1d3 /* SPORT2 receive primary A channel data buffer */ #define RX2B 0x1d4 /* SPORT2 receive secondary B channel data buffer */ #define DIV2 0x1d5 /* SPORT2 divisor for transmit/receive SLCK2 and FS2 */ #define CNT2 0x1d6 /* SPORT2 count register */ /* SPORT1 */ #define SPCTL1 0x1e0 /* SPORT1 serial port control register */ #define TX1A 0x1e1 /* SPORT1 serial port control register */ #define TX1B 0x1e2 /* SPORT1 transmit secondary B channel data buffer */ #define RX1A 0x1e3 /* SPORT1 receive primary A channel data buffer */ #define RX1B 0x1e4 /* SPORT1 receive secondary B channel data buffer */ #define DIV1 0x1e5 /* SPORT1 divisor for transmit/receive SLCK1 and FS1 */ #define CNT1 0x1e6 /* SPORT1 count register */ /* SPORT3 */ #define SPCTL3 0x1f0 /* SPORT3 serial port control register */ #define TX3A 0x1f1 /* SPORT3 serial port control register */ #define TX3B 0x1f2 /* SPORT3 transmit secondary B channel data buffer */ #define RX3A 0x1f3 /* SPORT3 receive primary A channel data buffer */ #define RX3B 0x1f4 /* SPORT3 receive secondary B channel data buffer */ #define DIV3 0x1f5 /* SPORT3 divisor for transmit/receive SLCK3 and FS3 */ #define CNT3 0x1f6 /* SPORT3 count register */ /* SPORT0 - MCM Receive (Works in pair with SPORT2) */ #define MR0CS0 0x1c7 /* SPORT0 multichannel rx select, channels 31 - 0 */ #define MR0CCS0 0x1c8 /* SPORT0 multichannel rx compand select, channels 31 - 0 */ #define MR0CS1 0x1c9 /* SPORT0 multichannel rx select, channels 63 - 32 */ #define MR0CCS1 0x1ca /* SPORT0 multichannel rx compand select, channels 63 - 32 */ #define MR0CS2 0x1cb /* SPORT0 multichannel rx select, channels 95 - 64 */ #define MR0CCS2 0x1cc /* SPORT0 multichannel rx compand select, channels 95 - 64 */ #define MR0CS3 0x1cd /* SPORT0 multichannel rx select, channels 127 - 96 */ #define MR0CCS3 0x1ce /* SPORT0 multichannel rx compand select, channels 127 - 96 */ /* SPORT2 - MCM Transmit (Works in pair with SPORT0) */ #define MT2CS0 0x1d7 /* SPORT2 multichannel tx select, channels 31 - 0 */ #define MT2CCS0 0x1d8 /* SPORT2 multichannel tx compand select, channels 31 - 0 */ #define MT2CS1 0x1d9 /* SPORT2 multichannel tx select, channels 63 - 32 */ #define MT2CCS1 0x1da /* SPORT2 multichannel tx compand select, channels 63 - 32 */ #define MT2CS2 0x1db /* SPORT2 multichannel tx select, channels 95 - 64 */ #define MT2CCS2 0x1dc /* SPORT2 multichannel tx compand select, channels 95 - 64 */ #define MT2CS3 0x1dd /* SPORT2 multichannel tx select, channels 127 - 96 */ #define MT2CCS3 0x1de /* SPORT2 multichannel tx compand select, channels 127 - 96 */ #define SP02MCTL 0x1df /* SPORTs 0 & 2 Multichannel Control Register */ /* SPORT1 - MCM Receive (Works in pair with SPORT3) */ #define MR1CS0 0x1e7 /* SPORT1 multichannel rx select, channels 31 - 0 */ #define MR1CCS0 0x1e8 /* SPORT1 multichannel rx compand select, channels 31 - 0 */ #define MR1CS1 0x1e9 /* SPORT1 multichannel rx select, channels 63 - 32 */ #define MR1CCS1 0x1ea /* SPORT1 multichannel rx compand select, channels 63 - 32 */ #define MR1CS2 0x1eb /* SPORT1 multichannel rx select, channels 95 - 64 */ #define MR1CCS2 0x1ec /* SPORT1 multichannel rx compand select, channels 95 - 64 */ #define MR1CS3 0x1ed /* SPORT1 multichannel rx select, channels 127 - 96 */ #define MR1CCS3 0x1ee /* SPORT1 multichannel rx compand select, channels 127 - 96 */ /* SPORT3 - MCM Transmit (Works in pair with SPORT1) */ #define MT3CS0 0x1f7 /* SPORT3 multichannel tx select, channels 31 - 0 */ #define MT3CCS0 0x1f8 /* SPORT3 multichannel tx compand select, channels 31 - 0 */ #define MT3CS1 0x1f9 /* SPORT3 multichannel tx select, channels 63 - 32 */ #define MT3CCS1 0x1fa /* SPORT3 multichannel tx compand select, channels 63 - 32 */ #define MT3CS2 0x1fb /* SPORT3 multichannel tx select, channels 95 - 64 */ #define MT3CCS2 0x1fc /* SPORT3 multichannel tx compand select, channels 95 - 64 */ #define MT3CS3 0x1fd /* SPORT3 multichannel tx select, channels 127 - 96 */ #define MT3CCS3 0x1fe /* SPORT3 multichannel tx compand select, channels 127 - 96 */ #define SP13MCTL 0x1ff /* SPORTs 1 & 3 Multichannel Control Register */ /*------ DMA Parameter Register Assignments - New Naming Conventions -------*/ /* DMA Channel 0 - Serial Port 0, A channel data */ #define II0A 0x60 /* Internal DMA0 memory address */ #define IM0A 0x61 /* Internal DMA0 memory access modifier */ #define C0A 0x62 /* Contains number of DMA0 transfers remaining */ #define CP0A 0x63 /* Points to next DMA0 parameters */ #define GP0A 0x64 /* DMA0 General purpose */ /* DMA Channel 1 - Serial Port 0, B channel data */ #define II0B 0x80 /* Internal DMA1 memory address */ #define IM0B 0x81 /* Internal DMA1 memory access modifier */ #define C0B 0x82 /* Contains number of DMA1 transfers remaining */ #define CP0B 0x83 /* Points to next DMA1 parameters */ #define GP0B 0x84 /* DMA1 General purpose */ /* DMA Channel 2 - Serial Port 1, A channel data */ #define II1A 0x68 /* Internal DMA2 memory address */ #define IM1A 0x69 /* Internal DMA2 memory access modifier */ #define C1A 0x6a /* Contains number of DMA2 transfers remaining */ #define CP1A 0x6b /* Points to next DMA2 parameters */ #define GP1A 0x6c /* DMA2 General purpose */ /* DMA Channel 3 - Serial Port 1, B channel data */ #define II1B 0x88 /* Internal DMA3 memory address */ #define IM1B 0x89 /* Internal DMA3 memory access modifier */ #define C1B 0x8a /* Contains number of DMA3 transfers remaining */ #define CP1B 0x8b /* Points to next DMA3 parameters */ #define GP1B 0x8c /* DMA3 General purpose */ /* DMA Channel 4 - Serial Port 2, A channel data */ #define II2A 0x70 /* Internal DMA4 memory address */ #define IM2A 0x71 /* Internal DMA4 memory access modifier */ #define C2A 0x72 /* Contains number of DMA4 transfers remaining */ #define CP2A 0x73 /* Points to next DMA4 parameters */ #define GP2A 0x74 /* DMA4 General purpose */ /* DMA Channel 5 - Serial Port 2, B channel data */ #define II2B 0x90 /* Internal DMA5 memory address */ #define IM2B 0x91 /* Internal DMA5 memory access modifier */ #define C2B 0x92 /* Contains number of DMA5 transfers remaining */ #define CP2B 0x93 /* Points to next DMA5 parameters */ #define GP2B 0x94 /* DMA5 General purpose */ /* DMA Channel 6 - Serial Port 3, A channel data */ #define II3A 0x78 /* Internal DMA6 memory address */ #define IM3A 0x79 /* Internal DMA6 memory access modifier */ #define C3A 0x7a /* Contains number of DMA6 transfers remaining */ #define CP3A 0x7b /* Points to next DMA6 parameters */ #define GP3A 0x7c /* DMA6 General purpose */ /* DMA Channel 7 - Serial Port 3, B channel data */ #define II3B 0x98 /* Internal DMA7 memory address */ #define IM3B 0x99 /* Internal DMA7 memory access modifier */ #define C3B 0x9a /* Contains number of DMA7 transfers remaining */ #define CP3B 0x9b /* Points to next DMA7 parameters */ #define GP3B 0x9c /* DMA7 General purpose */ /* DMA Channel 8 - Link Buffer 0 (or SPI Receive) */ #define IILB0 0x30 /* Internal DMA8 memory address */ #define IMLB0 0x31 /* Internal DMA8 memory access modifier */ #define CLB0 0x32 /* Contains number of DMA8 transfers remaining */ #define CPLB0 0x33 /* Points to next DMA8 parameters */ #define GPLB0 0x34 /* DMA8 General purpose */ /* DMA Channel 8 - SPI Receive (or Link Buffer 0) - No DMA Chain Pointer reg */ #define IISRX 0x30 /* Internal DMA8 memory address */ #define IMSRX 0x31 /* Internal DMA8 memory access modifier */ #define CSRX 0x32 /* Contains number of DMA8 transfers remaining */ #define GPSRX 0x34 /* DMA8 General purpose */ /* DMA Channel 9 - Link Buffer 1 (or SPI Transmit) */ #define IILB1 0x38 /* Internal DMA9 memory address */ #define IMLB1 0x39 /* Internal DMA9 memory access modifier */ #define CLB1 0x3a /* Contains number of DMA9 transfers remaining */ #define CPLB1 0x3b /* Points to next DMA9 parameters */ #define GPLB1 0x3c /* DMA9 General purpose */ /* DMA Channel 9 - SPI Transmit (or Link Buffer 1) - No DMA Chain Pointer reg */ #define IISTX 0x38 /* Internal DMA9 memory address */ #define IMSTX 0x39 /* Internal DMA9 memory access modifier */ #define CSTX 0x3a /* Contains number of DMA9 transfers remainnig */ #define GPSTX 0x3c /* DMA9 General purpose */ /* DMA Channel 10 - External Port FIFO Buffer 0 */ #define IIEP0 0x40 /* Internal DMA10 memory address */ #define IMEP0 0x41 /* Internal DMA10 memory access modifier */ #define CEP0 0x42 /* Contains number of DMA10 transfers remaining */ #define CPEP0 0x43 /* Points to next DMA10 parameters */ #define GPEP0 0x44 /* DMA10 General purpose */ #define EIEP0 0x45 /* External DMA10 address */ #define EMEP0 0x46 /* External DMA10 address modifier */ #define ECEP0 0x47 /* External DMA10 counter */ /* DMA Channel 11 - External Port FIFO Buffer 1 */ #define IIEP1 0x48 /* Internal DMA11 memory address */ #define IMEP1 0x49 /* Internal DMA11 memory access modifier */ #define CEP1 0x4a /* Contains number of DMA11 transfers remaining */ #define CPEP1 0x4b /* Points to next DMA11 parameters */ #define GPEP1 0x4c /* DMA11 General purpose */ #define EIEP1 0x4d /* External DMA11 address */ #define EMEP1 0x4e /* External DMA11 address modifier */ #define ECEP1 0x4f /* External DMA counter */ /* DMA Channel 12 - External Port FIFO Buffer 2 */ #define IIEP2 0x50 /* Internal DMA12 memory address */ #define IMEP2 0x51 /* Internal DMA12 memory access modifier */ #define CEP2 0x52 /* Contains number of DMA12 transfers remaining */ #define CPEP2 0x53 /* Points to next DMA12 parameters */ #define GPEP2 0x54 /* DMA12 General purpose */ #define EIEP2 0x55 /* External DMA12 address */ #define EMEP2 0x56 /* External DMA12 address modifier */ #define ECEP2 0x57 /* External DMA12 counter */ /* DMA Channel 13 - External Port FIFO Buffer 3 */ #define IIEP3 0x58 /* Internal DMA13 memory address */ #define IMEP3 0x59 /* Internal DMA13 memory access modifier */ #define CEP3 0x5a /* Contains number of DMA13 transfers remaining */ #define CPEP3 0x5b /* Points to next DMA13 parameters */ #define GPEP3 0x5c /* DMA13 General purpose */ #define EIEP3 0x5d /* External DMA13 address */ #define EMEP3 0x5e /* External DMA13 address modifier */ #define ECEP3 0x5f /* External DMA13 counter */ /*---- DMA Parameter Register Assignments - Old Legacy ADSP-21160 Naming Conventions ---- */ /* NOTE: For backwards compatibility, we can retain the old DMA parameter register names used in the ADSP-21160. However, the naming conventions used for DMA channels of the ADSP-21160 do not necessarily correspond to the actual DMA channel priority assigment for the ADSP-21160 Ex) DMA Channel 4 IOP addresses on the ADSP-21160 are now DMA channel 8 on the ADSP-21161 DMA Channel 5 IOP addresses on the ADSP-21160 are now DMA channel 9 on the ADSP-21161 To clear any confusion, we recommend using the new IOP naming conventions for the DMA parameter registers as defined above */ #define II0 0x60 /* Internal DMA0 memory address */ #define IM0 0x61 /* Internal DMA0 memory access modifier */ #define C0 0x62 /* Contains number of DMA0 transfers remaining */ #define CP0 0x63 /* Points to next DMA0 parameters */ #define GP0 0x64 /* DMA0 General purpose */ #define II1 0x68 /* Internal DMA1 memory address */ #define IM1 0x69 /* Internal DMA1 memory access modifier */ #define C1 0x6a /* Contains number of DMA1 transfers remaining */ #define CP1 0x6b /* Points to next DMA1 parameters */ #define GP1 0x6c /* DMA1 General purpose */ #define II2 0x70 /* Internal DMA2 memory address */ #define IM2 0x71 /* Internal DMA2 memory access modifier */ #define C2 0x72 /* Contains number of DMA2 transfers remaining */ #define CP2 0x73 /* Points to next DMA2 parameters */ #define GP2 0x74 /* DMA2 General purpose */ #define II3 0x78 /* Internal DMA3 memory address */ #define IM3 0x79 /* Internal DMA3 memory access modifier */ #define C3 0x7a /* Contains number of DMA3 transfers remaining */ #define CP3 0x7b /* Points to next DMA3 parameters */ #define GP3 0x7c /* DMA3 General purpose */ #define II6 0x80 /* Internal DMA6 memory address */ #define IM6 0x81 /* Internal DMA6 memory access modifier */ #define C6 0x82 /* Contains number of DMA6 transfers remaining */ #define CP6 0x83 /* Points to next DMA6 parameters */ #define GP6 0x84 /* DMA6 General purpose */ #define II7 0x88 /* Internal DMA7 memory address */ #define IM7 0x89 /* Internal DMA7 memory access modifier */ #define C7 0x8a /* Contains number of DMA7 transfers remaining */ #define CP7 0x8b /* Points to next DMA7 parameters */ #define GP7 0x8c /* DMA7 General purpose */ #define II8 0x90 /* Internal DMA8 memory address */ #define IM8 0x91 /* Internal DMA8 memory access modifier */ #define C8 0x92 /* Contains number of DMA8 transfers remaining */ #define CP8 0x93 /* Points to next DMA8 parameters */ #define GP8 0x94 /* DMA8 General Purpose */ #define II9 0x98 /* Internal DMA9 memory address */ #define IM9 0x99 /* Internal DMA9 memory access modifier */ #define C9 0x9a /* Contains number of DMA9 transfers remaining */ #define CP9 0x9b /* Points to next DMA9 parameters */ #define GP9 0x9c /* DMA9 General purpose */ #define II4 0x30 /* Internal DMA4 memory address */ #define IM4 0x31 /* Internal DMA4 memory access modifier */ #define C4 0x32 /* Contains number of DMA4 transfers remaining */ #define CP4 0x33 /* Points to next DMA4 parameters */ #define GP4 0x34 /* DMA4 General purpose */ #define II5 0x38 /* Internal DMA5 memory address */ #define IM5 0x39 /* Internal DMA5 memory access modifier */ #define C5 0x3a /* Contains number of DMA5 transfers remaining */ #define CP5 0x3b /* Points to next DMA5 parameters */ #define GP5 0x3c /* DMA5 General purpose */ #define II10 0x40 /* Internal DMA10 memory address */ #define IM10 0x41 /* Internal DMA10 memory access modifier */ #define C10 0x42 /* Contains number of DMA10 transfers remaining */ #define CP10 0x43 /* Points to next DMA10 parameters */ #define GP10 0x44 /* DMA10 General purpose */ #define EI10 0x45 /* External DMA10 address */ #define EM10 0x46 /* External DMA10 address modifier */ #define EC10 0x47 /* External DMA10 counter */ #define II11 0x48 /* Internal DMA11 memory address */ #define IM11 0x49 /* Internal DMA11 memory access modifier */ #define C11 0x4a /* Contains number of DMA11 transfers remaining */ #define CP11 0x4b /* Points to next DMA11 parameters */ #define GP11 0x4c /* DMA11 General purpose */ #define EI11 0x4d /* External DMA11 address */ #define EM11 0x4e /* External DMA11 address modifier */ #define EC11 0x4f /* External DMA counter */ #define II12 0x50 /* Internal DMA12 memory address */ #define IM12 0x51 /* Internal DMA12 memory access modifier */ #define C12 0x52 /* Contains number of DMA12 transfers remaining */ #define CP12 0x53 /* Points to next DMA12 parameters */ #define GP12 0x54 /* DMA12 General purpose */ #define EI12 0x55 /* External DMA12 address */ #define EM12 0x56 /* External DMA12 address modifier */ #define EC12 0x57 /* External DMA12 counter */ #define II13 0x58 /* Internal DMA13 memory address */ #define IM13 0x59 /* Internal DMA13 memory access modifier */ #define C13 0x5a /* Contains number of DMA13 transfers remaining */ #define CP13 0x5b /* Points to next DMA13 parameters */ #define GP13 0x5c /* DMA13 General purpose */ #define EI13 0x5d /* External DMA13 address */ #define EM13 0x5e /* External DMA13 address modifier */ #define EC13 0x5f /* External DMA13 counter */ /* Emulation/Breakpoint Registers (remapped from UREG space) */ /* NOTES: - These registers are ONLY accessible by the core - It is *highly* recommended that these facilities be accessed only through the ADI emulator routines */ /* Core Emulation HWBD Registers */ #define PSA1S 0xa0 /* Instruction address start #1 */ #define PSA1E 0xa1 /* Instruction address end #1 */ #define PSA2S 0xa2 /* Instruction address start #2 */ #define PSA2E 0xa3 /* Instruction address end #2 */ #define PSA3S 0xa4 /* Instruction address start #3 */ #define PSA3E 0xa5 /* Instruction address end #3 */ #define PSA4S 0xa6 /* Instruction address start #4 */ #define PSA4E 0xa7 /* Instruction address end #4 */ #define PMDAS 0xa8 /* Program Data address start */ #define PMDAE 0xa9 /* Program Data address end */ #define DMA1S 0xaa /* Data address start #1 */ #define DMA1E 0xab /* Data address end #1 */ #define DMA2S 0xac /* Data address start #2 */ #define DMA2E 0xad /* Data address end #2 */ #define EMUN 0xae /* hwbp hit-count register */ /* IOP Emulation HWBP Bounds Registers */ #define IOAS 0xb0 /* IOA Upper Bounds Register */ #define IOAE 0xb1 /* IOA Lower Bounds Register */ #define EPAS 0xb2 /* EPA Upper Bounds Register */ #define EPAE 0xb3 /* EPA Lower Bounds Register */ /*----------------------------------------------------------------------------*/ /* System Register bit definitions */ /*----------------------------------------------------------------------------*/ /* MODE1 and MMASK registers */ #define BR8 BIT_0 /* Bit 0: Bit-reverse for I8 */ #define BR0 BIT_1 /* Bit 1: Bit-reverse for I0 (uses DMS0- only ) */ #define SRCU BIT_2 /* Bit 2: Alt. register select for comp. units */ #define SRD1H BIT_3 /* Bit 3: DAG1 alt. register select (7-4) */ #define SRD1L BIT_4 /* Bit 4: DAG1 alt. register select (3-0) */ #define SRD2H BIT_5 /* Bit 5: DAG2 alt. register select (15-12) */ #define SRD2L BIT_6 /* Bit 6: DAG2 alt. register select (11-8) */ #define SRRFH BIT_7 /* Bit 7: Register file alt. select for R(15-8) */ #define SRRFL BIT_10 /* Bit 10: Register file alt. select for R(7-0) */ #define NESTM BIT_11 /* Bit 11: Interrupt nesting enable */ #define IRPTEN BIT_12 /* Bit 12: Global interrupt enable */ #define ALUSAT BIT_13 /* Bit 13: Enable ALU fixed-pt. saturation */ #define SSE BIT_14 /* Bit 14: Enable short word sign extension */ #define TRUNCATE BIT_15 /* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest */ #define RND32 BIT_16 /* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd */ #define CSEL (BIT_17|BIT_18) /* Bit 17-18: CSelect: Bus Mastership */ #define PEYEN BIT_21 /* Bit 21: Processing Element Y enable */ #define SIMD BIT_21 /* Bit 21: Enable SIMD Mode */ #define BDCST9 BIT_22 /* Bit 22: Load Broadcast for I9 */ #define BDCST1 BIT_23 /* Bit 23: Load Broadcast for I1 */ #define CBUFEN BIT_24 /* Bit 23: Circular Buffer Enable */ /* MODE2 register */ #define IRQ0E BIT_0 /* Bit 0: IRQ0- 1=edge sens. 0=level sens. */ #define IRQ1E BIT_1 /* Bit 1: IRQ1- 1=edge sens. 0=level sens. */ #define IRQ2E BIT_2 /* Bit 2: IRQ2- 1=edge sens. 0=level sens. */ #define CADIS BIT_4 /* Bit 4: Cache disable */ #define TIMEN BIT_5 /* Bit 5: Timer enable */ #define BUSLK BIT_6 /* Bit 6: External bus lock */ #define FLG0O BIT_15 /* Bit 15: FLAG0 1=output 0=input */ #define FLG1O BIT_16 /* Bit 16: FLAG1 1=output 0=input */ #define FLG2O BIT_17 /* Bit 17: FLAG2 1=output 0=input */ #define FLG3O BIT_18 /* Bit 18: FLAG3 1=output 0=input */ #define CAFRZ BIT_19 /* Bit 19: Cache freeze */ #define IIRAE BIT_20 /* Bit 20: Illegal IOP Register Access Enable */ #define U64MAE BIT_21 /* Bit 21: Unaligned 64-bit Memory Access Enable */ /* bits 31-30, 27-25 are Processor Type[4:0], read only, value: 0b01001 bits 29-28 are silicon revision[1:0], read only, value: 0 These bits (only) are routed to Mode2 Shadow register (IOP register 0x11) */ /* FLAGS register */ #define FLG0 BIT_0 /* Bit 0: FLAG0 value */ #define FLG1 BIT_1 /* Bit 1: FLAG1 value */ #define FLG2 BIT_2 /* Bit 2: FLAG2 value */ #define FLG3 BIT_3 /* Bit 3: FLAG3 value */ /* ASTATx and ASTATy registers */ #ifdef SUPPORT_DEPRECATED_USAGE /* Several of these (AV, AC, MV, SV, SZ) are assembler-reserved keywords, so this style is now deprecated. If these are defined, the assembler- reserved keywords are still available in lowercase, e.g., IF sz JUMP LABEL1. */ # define AZ BIT_0 /* Bit 0: ALU result zero or fltg-pt. underflow */ # define AV BIT_1 /* Bit 1: ALU overflow */ # define AN BIT_2 /* Bit 2: ALU result negative */ # define AC BIT_3 /* Bit 3: ALU fixed-pt. carry */ # define AS BIT_4 /* Bit 4: ALU X input sign (ABS and MANT ops) */ # define AI BIT_5 /* Bit 5: ALU fltg-pt. invalid operation */ # define MN BIT_6 /* Bit 6: Multiplier result negative */ # define MV BIT_7 /* Bit 7: Multiplier overflow */ # define MU BIT_8 /* Bit 8: Multiplier fltg-pt. underflow */ # define MI BIT_9 /* Bit 9: Multiplier fltg-pt. invalid operation */ # define AF BIT_10 /* Bit 10: ALU fltg-pt. operation */ # define SV BIT_11 /* Bit 11: Shifter overflow */ # define SZ BIT_12 /* Bit 12: Shifter result zero */ # define SS BIT_13 /* Bit 13: Shifter input sign */ # define BTF BIT_18 /* Bit 18: Bit test flag for system registers */ # define CACC0 BIT_24 /* Bit 24: Compare Accumulation Bit 0 */ # define CACC1 BIT_25 /* Bit 25: Compare Accumulation Bit 1 */ # define CACC2 BIT_26 /* Bit 26: Compare Accumulation Bit 2 */ # define CACC3 BIT_27 /* Bit 27: Compare Accumulation Bit 3 */ # define CACC4 BIT_28 /* Bit 28: Compare Accumulation Bit 4 */ # define CACC5 BIT_29 /* Bit 29: Compare Accumulation Bit 5 */ # define CACC6 BIT_30 /* Bit 30: Compare Accumulation Bit 6 */ # define CACC7 BIT_31 /* Bit 31: Compare Accumulation Bit 7 */ #endif #define ASTAT_AZ BIT_0 /* Bit 0: ALU result zero or fltg-pt. u'flow*/ #define ASTAT_AV BIT_1 /* Bit 1: ALU overflow */ #define ASTAT_AN BIT_2 /* Bit 2: ALU result negative */ #define ASTAT_AC BIT_3 /* Bit 3: ALU fixed-pt. carry */ #define ASTAT_AS BIT_4 /* Bit 4: ALU X input sign(ABS and MANT ops)*/ #define ASTAT_AI BIT_5 /* Bit 5: ALU fltg-pt. invalid operation */ #define ASTAT_MN BIT_6 /* Bit 6: Multiplier result negative */ #define ASTAT_MV BIT_7 /* Bit 7: Multiplier overflow */ #define ASTAT_MU BIT_8 /* Bit 8: Multiplier fltg-pt. underflow */ #define ASTAT_MI BIT_9 /* Bit 9: Multiplier fltg-pt. invalid op. */ #define ASTAT_AF BIT_10 /* Bit 10: ALU fltg-pt. operation */ #define ASTAT_SV BIT_11 /* Bit 11: Shifter overflow */ #define ASTAT_SZ BIT_12 /* Bit 12: Shifter result zero */ #define ASTAT_SS BIT_13 /* Bit 13: Shifter input sign */ #define ASTAT_BTF BIT_18 /* Bit 18: Bit test flag for system registers*/ #define ASTAT_CACC0 BIT_24 /* Bit 24: Compare Accumulation Bit 0 */ #define ASTAT_CACC1 BIT_25 /* Bit 25: Compare Accumulation Bit 1 */ #define ASTAT_CACC2 BIT_26 /* Bit 26: Compare Accumulation Bit 2 */ #define ASTAT_CACC3 BIT_27 /* Bit 27: Compare Accumulation Bit 3 */ #define ASTAT_CACC4 BIT_28 /* Bit 28: Compare Accumulation Bit 4 */ #define ASTAT_CACC5 BIT_29 /* Bit 29: Compare Accumulation Bit 5 */ #define ASTAT_CACC6 BIT_30 /* Bit 30: Compare Accumulation Bit 6 */ #define ASTAT_CACC7 BIT_31 /* Bit 31: Compare Accumulation Bit 7 */ /* STKYx and STKYy registers */ /* bits 0 to 9 in both STKYx and STKYY, bits 17 to 26 in STKYx only */ #define AUS BIT_0 /* Bit 0: ALU fltg-pt. underflow */ #define AVS BIT_1 /* Bit 1: ALU fltg-pt. overflow */ #define AOS BIT_2 /* Bit 2: ALU fixed-pt. overflow */ #define AIS BIT_5 /* Bit 5: ALU fltg-pt. invalid operation */ #define MOS BIT_6 /* Bit 6: Multiplier fixed-pt. overflow */ #define MVS BIT_7 /* Bit 7: Multiplier fltg-pt. overflow */ #define MUS BIT_8 /* Bit 8: Multiplier fltg-pt. underflow */ #define MIS BIT_9 /* Bit 9: Multiplier fltg-pt. invalid operation */ /* STKYx register *ONLY* */ #define CB7S BIT_17 /* Bit 17: DAG1 circular buffer 7 overflow */ #define CB15S BIT_18 /* Bit 18: DAG2 circular buffer 15 overflow */ #define IIRA BIT_19 /* Bit 19: Illegal IOP Register Access */ #define U64MA BIT_20 /* Bit 20: Unaligned 64-bit Memory Access */ #define PCFL BIT_21 /* Bit 21: PC stack full */ #define PCEM BIT_22 /* Bit 22: PC stack empty */ #define SSOV BIT_23 /* Bit 23: Status stack overflow (MODE1 and ASTAT) */ #define SSEM BIT_24 /* Bit 24: Status stack empty */ #define LSOV BIT_25 /* Bit 25: Loop stack overflow */ #define LSEM BIT_26 /* Bit 26: Loop stack empty */ /* IRPTL and IMASK and IMASKP registers */ #define EMUI BIT_0 /* Bit 0: Offset: 00: Emulator Interrupt */ #define RSTI BIT_1 /* Bit 1: Offset: 04: Reset */ #define IICDI BIT_2 /* Bit 2: Offset: 08: Illegal Input Condition Detected */ #define SOVFI BIT_3 /* Bit 3: Offset: 0c: Stack overflow */ #define TMZHI BIT_4 /* Bit 4: Offset: 10: Timer = 0 (high priority) */ #define VIRPTI BIT_5 /* Bit 5: Offset: 14: Vector interrupt */ #define IRQ2I BIT_6 /* Bit 6: Offset: 18: IRQ2- asserted */ #define IRQ1I BIT_7 /* Bit 7: Offset: 1c: IRQ1- asserted */ #define IRQ0I BIT_8 /* Bit 8: Offset: 20: IRQ0- asserted */ #define SP0I BIT_10 /* Bit 10: Offset: 28: SPORT0 DMA channel */ #define SP1I BIT_11 /* Bit 11: Offset: 2c: SPORT1 DMA channel */ #define SP2I BIT_12 /* Bit 12: Offset: 30: SPORT2 DMA channel */ #define SP3I BIT_13 /* Bit 13: Offset: 34: SPORT3 DMA channel */ #define LPISUMI BIT_14 /* Bit 14: Offset: na: LPort Interrupt Summary */ #define EP0I BIT_15 /* Bit 15: Offset: 50: External port channel 0 DMA */ #define EP1I BIT_16 /* Bit 16: Offset: 54: External port channel 1 DMA */ #define EP2I BIT_17 /* Bit 17: Offset: 58: External port channel 2 DMA */ #define EP3I BIT_18 /* Bit 18: Offset: 5c: External port channel 3 DMA */ #define LSRQI BIT_19 /* Bit 19: Offset: 60: Link service request */ #define CB7I BIT_20 /* Bit 20: Offset: 64: Circ. buffer 7 overflow */ #define CB15I BIT_21 /* Bit 21: Offset: 68: Circ. buffer 15 overflow */ #define TMZLI BIT_22 /* Bit 22: Offset: 6c: Timer = 0 (low priority) */ #define FIXI BIT_23 /* Bit 23: Offset: 70: Fixed-pt. overflow */ #define FLTOI BIT_24 /* Bit 24: Offset: 74: fltg-pt. overflow */ #define FLTUI BIT_25 /* Bit 25: Offset: 78: fltg-pt. underflow */ #define FLTII BIT_26 /* Bit 26: Offset: 7c: fltg-pt. invalid */ #define SFT0I BIT_27 /* Bit 27: Offset: 80: user software int 0 */ #define SFT1I BIT_28 /* Bit 28: Offset: 84: user software int 1 */ #define SFT2I BIT_29 /* Bit 39: Offset: 88: user software int 2 */ #define SFT3I BIT_30 /* Bit 30: Offset: 8c: user software int 3 */ /* LIRPTL register */ #define LP0I BIT_0 /* Bit 0: Offset: 38: Link port channel 0 DMA */ #define LP1I BIT_1 /* Bit 1: Offset: 3C: Link port channel 1 DMA */ #define SPIRI BIT_2 /* Bit 2: Offset: 40: SPI Receive DMA */ #define SPITI BIT_3 /* Bit 3: Offset: 44: SPI Transmit DMA */ #define LP0MSK BIT_16 /* Bit 16: Link port channel 0 Interrupt Mask */ #define LP1MSK BIT_17 /* Bit 17: Link port channel 1 Interrupt Mask */ #define SPIRMSK BIT_18 /* Bit 18: SPI Receive Interrupt Mask */ #define SPITMSK BIT_19 /* Bit 19: SPI Transmit Interrupt Mask */ #define LP0MSKP BIT_24 /* Bit 24: Link port channel 0 Interrupt Mask Pointer */ #define LP1MSKP BIT_25 /* Bit 25: Link port channel 1 Interrupt Mask Pointer */ #define SPIRMSKP BIT_26 /* Bit 26: SPI Receive Interrupt Mask Pointer */ #define SPITMSKP BIT_27 /* Bit 27: SPI Transmit Interrupt Mask Pointer */ /* LSRQ register */ #define L0TM BIT_4 /* Link Port 0 Transmit Mask */ #define L0RM BIT_5 /* Link Port 0 Receive Mask */ #define L1TM BIT_6 /* Link Port 1 Transmit Mask */ #define L1RM BIT_7 /* Link Port 1 Receive Mask */ #define L0TRQ BIT_20 /* Link Port 0 Transmit Request */ #define L0RRQ BIT_21 /* Link Port 1 Receive Request */ #define L1TRQ BIT_22 /* Link Port 0 Transmit Request */ #define L1RRQ BIT_23 /* Link Port 1 Receive Request */ /*----------------------------------------------------------------------------*/ /* */ /* IOP Control/Status Register Bit Definitions */ /* */ /*----------------------------------------------------------------------------*/ /* SYSCON Register */ #define SRST BIT_0 /* Soft Reset */ #define BSO BIT_1 /* Boot Select Override */ #define IIVT BIT_2 /* Internal Interrupt Vector Table */ #define IWT BIT_3 /* Instruction word transfer (0 = data, 1 = inst) */ #define HBW32 0x00000000 /* Host bus width: 32 */ #define HBW16 BIT_4 /* Host bus width: 16 */ #define HBW8 BIT_5 /* Host bus width: 8 */ #define HMSWF BIT_7 /* Host packing order (0 = LSW first, 1 = MSW) */ #define HPFLSH BIT_8 /* Host pack flush */ #define IMDW0X BIT_9 /* Internal memory block 0, extended data (40 bit) */ #define IMDW1X BIT_10 /* Internal memory block 1, extended data (40 bit) */ #define ADREDY BIT_11 /* Active Drive Ready */ #define BHD BIT_16 /* Buffer Hand Disable */ #define EBPR00 0x00000000 /* External bus priority: Even */ #define EBPR01 BIT_17 /* External bus priority: Core has priority */ #define EBPR10 BIT_18 /* External bus priority: IO has priority */ #define DCPR BIT_19 /* Select rotating access priority on DMA10 - DMA13 */ #define LDCPR BIT_20 /* Select rotating access priority on DMA8 - DMA9 */ #define PRROT BIT_21 /* Select rotating prio between LPort and EPort */ #define COD BIT_22 /* Clock Out Disable */ #define IPACK0 BIT_30 /* External instruction execution packing mode bit 0 */ #define IPACK1 BIT_31 /* External instruction execution packing mode bit 1 */ /* SYSTAT Register */ #define HSTM BIT_0 /* Host is the Bus Master */ #define BSYN BIT_1 /* Bus arbitration logic is synchronized */ #define CRBM (BIT_4|BIT_5|BIT_6) /* Current ADSP211xx Bus Master */ #define IDC (BIT_8|BIT_9|BIT_10) /* ADSP211xx ID Code */ #define VIPD BIT_13 /* Vector interrupt pending (1 = pending) */ #define CRAT (BIT_16|BIT_17|BIT_18) /* CLK_CFG(3-0), Core:CLKIN clock ratio */ #define SSWPD BIT_20 /* Sync slave write pending... SSWPD bit added for 21161 */ #define SWPD BIT_21 /* Any (sync + Async) slave write pending */ #define HPS (BIT_22|BIT_23|BIT_24) /* Host pack status... HPS modified for 21161 */ /* MODE2_SHDW Register - IOP register adrees 0x11 */ /* bits 31-30, 27-25 are Processor ID[4:0], read only, value: 01010 bits 29-28 are silicon revision[1:0], read only, value: 01 These former MODE2 register bitfields (only) are now routed to the MODE2 Shadow register (IOP register 0x11). Bits 25-31 now reserved in MODE2. */ #define PID20 (BIT_25|BIT_26|BIT_27) /* PID[2:0] Processor Identification (read-only) */ #define SIREV (BIT_28|BIT_29) /* Silicon Revision (read-only) */ #define PID43 (BIT_30|BIT_31) /* PID[4:3] Processor Identification (read-only) */ /* WAIT Register */ /* generic WAIT bitfields */ #define EB0AM (BIT_0|BIT_1) /* External Bank 0 Access Mode */ #define EB0WS (BIT_2|BIT_3|BIT_4) /* External Bank 0 Waitstate Configuration */ #define EB1AM (BIT_5|BIT_6) /* External Bank 1 Access Mode */ #define EB1WS (BIT_7|BIT_8|BIT_9) /* External Bank 1 Waitstate Configuration */ #define EB2AM (BIT_10|BIT_11) /* External Bank 1 Access Mode */ #define EB2WS (BIT_12|BIT_13|BIT_14) /* External Bank 2 Waitstate Configuration */ #define EB3AM (BIT_15|BIT_16) /* External Bank 1 Access Mode */ #define EB3WS (BIT_17|BIT_18|BIT_19) /* External Bank 3 Waitstate Configuration */ #define RBAM (BIT_20|BIT_21) /* ROM Boot Access Mode */ #define RBWS (BIT_22|BIT_23|BIT_24) /* ROM Boot Waitstate Configuration */ #define HIDMA BIT_30 /* Single idle cycle for DMA handshake */ /* specific wait access mode settings */ #define EB0A0 0x00000000 /* Ext Bank 0 Async, internal AND external ACK */ #define EB0S1 BIT_0 /* Ext Bank 0 Sync, 2-cycle reads, 1-cycle writes */ #define EB0S2 BIT_1 /* Ext Bank 0 Sync, 2-cycle reads, 2-cycle writes */ #define EB1A0 0x00000000 /* Ext Bank 1 Async, internal AND external ACK */ #define EB1S1 BIT_5 /* Ext Bank 1 Sync, 2-cycle reads, 1-cycle writes */ #define EB1S2 BIT_6 /* Ext Bank 1 Sync, 2-cycle reads, 2-cycle writes */ #define EB2A0 0x00000000 /* Ext Bank 2 Async, internal AND external ACK */ #define EB2S1 BIT_10 /* Ext Bank 2 Sync, 2-cycle reads, 1-cycle writes */ #define EB2S2 BIT_11 /* Ext Bank 2 Sync, 2-cycle reads, 2-cycle writes */ #define EB3A0 0x00000000 /* Ext Bank 3 Async, internal AND external ACK */ #define EB3S1 BIT_15 /* Ext Bank 3 Sync, 2-cycle reads, 1-cycle writes */ #define EB3S2 BIT_16 /* Ext Bank 3 Sync, 2-cycle reads, 2-cycle writes */ #define RBWA0 0x00000000 /* ROM boot: Async, internal AND external ACK */ #define RBWS1 BIT_20 /* ROM boot: Sync, 2-cycle reads, 1-cycle writes */ #define RBWS2 BIT_21 /* ROM boot: Sync, 2-cycle reads, 2-cycle writes */ /* individual waitstate combinations */ #define EB0WS0 0x00000000 /* External Bank 0: 0 waitstates, no hold cycle */ #define EB0WS1 BIT_2 /* External Bank 0: 1 waitstates, no hold cycle */ #define EB0WS2 BIT_3 /* External Bank 0: 2 waitstates, hold cycle */ #define EB0WS3 (BIT_2|BIT_3) /* External Bank 0: 3 waitstates, hold cycle */ #define EB0WS4 BIT_4 /* External Bank 0: 4 waitstates, hold cycle */ #define EB0WS5 (BIT_2|BIT_4) /* External Bank 0: 5 waitstates, hold cycle */ #define EB0WS6 (BIT_3|BIT_4) /* External Bank 0: 6 waitstates, hold cycle */ #define EB0WS7 (BIT_2|BIT_3|BIT_4) /* External Bank 0: 7 waitstates, hold cycle */ #define EB1WS0 0x00000000 /* External Bank 1: 0 waitstates, no hold cycle */ #define EB1WS1 BIT_7 /* External Bank 1: 1 waitstates, no hold cycle */ #define EB1WS2 BIT_8 /* External Bank 1: 2 waitstates, hold cycle */ #define EB1WS3 (BIT_7|BIT_8) /* External Bank 1: 3 waitstates, hold cycle */ #define EB1WS4 BIT_9 /* External Bank 1: 4 waitstates, hold cycle */ #define EB1WS5 (BIT_7|BIT_9) /* External Bank 1: 5 waitstates, hold cycle */ #define EB1WS6 (BIT_8|BIT_9) /* External Bank 1: 6 waitstates, hold cycle */ #define EB1WS7 (BIT_7|BIT_8|BIT_9) /* External Bank 1: 7 waitstates, hold cycle */ #define EB2WS0 0x00000000 /* External Bank 2: 0 waitstates, no hold cycle */ #define EB2WS1 BIT_12 /* External Bank 2: 1 waitstates, no hold cycle */ #define EB2WS2 BIT_13 /* External Bank 2: 2 waitstates, hold cycle */ #define EB2WS3 (BIT_12|BIT_13) /* External Bank 2: 3 waitstates, hold cycle */ #define EB2WS4 BIT_14 /* External Bank 2: 4 waitstates, hold cycle */ #define EB2WS5 (BIT_12|BIT_14) /* External Bank 2: 5 waitstates, hold cycle */ #define EB2WS6 (BIT_13|BIT_14) /* External Bank 2: 6 waitstates, hold cycle */ #define EB2WS7 (BIT_12|BIT_13|BIT_14) /* External Bank 2: 7 waitstates, hold cycle */ #define EB3WS0 0x00000000 /* External Bank 3: 0 waitstates, no hold cycle */ #define EB3WS1 BIT_17 /* External Bank 3: 1 waitstates, no hold cycle */ #define EB3WS2 BIT_18 /* External Bank 3: 2 waitstates, hold cycle */ #define EB3WS3 (BIT_17|BIT_18) /* External Bank 3: 3 waitstates, hold cycle */ #define EB3WS4 BIT_19 /* External Bank 3: 4 waitstates, hold cycle */ #define EB3WS5 (BIT_17|BIT_19) /* External Bank 3: 5 waitstates, hold cycle */ #define EB3WS6 (BIT_18|BIT_19) /* External Bank 3: 6 waitstates, hold cycle */ #define EB3WS7 (BIT_17|BIT_18|BIT_19) /* External Bank 3: 7 waitstates, hold cycle */ #define RBWST0 0x00000000 /* ROM boot wait state 0, no hold cycle */ #define RBWST1 BIT_22 /* ROM boot wait state 1, no hold cycle */ #define RBWST2 BIT_23 /* ROM boot wait state 2, hold cycle */ #define RBWST3 (BIT_22|BIT_23) /* ROM boot wait state 3, hold cycle */ #define RBWST4 BIT_24 /* ROM boot wait state 4, hold cycle */ #define RBWST5 (BIT_22|BIT_24) /* ROM boot wait state 5, hold cycle */ #define RBWST6 (BIT_23|BIT_24) /* ROM boot wait state 6, hold cycle */ #define RBWST7 (BIT_22|BIT_23|BIT_24) /* ROM boot wait state 7, hold cycle */ /* DMAC10, DMAC11, DMAC12, DMAC13 Register Bitfield Definitions */ #define DEN BIT_0 /* External Port DMA Enable */ #define CHEN BIT_1 /* External Port DMA Chaining Enable */ #define TRAN BIT_2 /* External Port EPBx Transmit/Receive Select */ #define DTYPE BIT_5 /* EPBx FIFO Buffer Data Type Select */ #define PMODE1 BIT_6 /* EPBx FIFO Packing Modes... 16-bit external to 32/64-bit internal packing */ #define PMODE2 BIT_7 /* 16-bit external to 48-bit internal packing */ #define PMODE3 (BIT_6|BIT_7) /* 32-bit external to 48-bit internal packing */ #define PMODE4 BIT_8 /* No Pack Mode - 32-bit external to 32/64-bit internal packing */ #define PMODE5 (BIT_6|BIT_8) /* 8-bit external to 48-bit internal packing */ #define PMODE6 (BIT_7|BIT_8) /* 8-bit external to 32/64-bit internal packing */ #define MSWF BIT_9 /* Most Significant Word First During Packing */ #define MASTER BIT_10 /* EPBx DMA Master Mode Enable */ #define HSHAKE BIT_11 /* EPBx DMA Handshake Mode Enable */ #define INTIO BIT_12 /* Single Word Interrupts for EPBx FIFO Buffers */ #define EXT_HANDSHAKE_EN BIT_13 /* External Handshake Mode Enable */ #define FLSH BIT_14 /* Flush EPBx FIFO Buffers and Status */ #define PRIO BIT_15 /* External Port Bus Priority Access */ #define FS (BIT_16|BIT_17) /* External Port FIFO Buffer Status (read-only) */ #define INT32 BIT_18 /* Internal Memory 32-bit Transfer Select */ #define MAXBL0 BIT_19 /* Maximum Burst Length Select Disabled */ #define MAXBL1 BIT_20 /* Maximum Burst Length Limit of 4 Enabled */ #define PS (BIT_21|BIT_22|BIT_23) /* External Port EPBx FIFO Buffer Packing Status (read-only) */ /* DMASTAT Register (read-only) */ #define DMA0ST BIT_0 /* DMA channel 0 (RX0A/TX0A) Active Status */ #define DMA2ST BIT_1 /* DMA channel 2 (RX1A/TX1A) Active Status */ #define DMA4ST BIT_2 /* DMA channel 4 (RX2A/TX2A) Active Status */ #define DMA6ST BIT_3 /* DMA channel 6 (RX3A/TX3A) Active Status */ #define DMA8ST BIT_4 /* DMA channel 8 (LBUF0) Active Status */ #define DMA9ST BIT_5 /* DMA channel 9 (LBUF1) Active Status */ #define DMA1ST BIT_6 /* DMA channel 1 (RX0B/TX0B) Active Status */ #define DMA3ST BIT_7 /* DMA channel 3 (RX1B/TX1B) Active Status */ #define DMA5ST BIT_8 /* DMA channel 5 (RX2B/TX2B) Active Status */ #define DMA7ST BIT_9 /* DMA channel 7 (RX3B/TX3B) Active Status */ #define DMA10ST BIT_10 /* DMA channel 10 (EPB0) Active Status */ #define DMA11ST BIT_11 /* DMA channel 11 (EPB1) Active Status */ #define DMA12ST BIT_12 /* DMA channel 12 (EPB2) Active Status */ #define DMA13ST BIT_13 /* DMA channel 13 (EPB3) Active Status */ #define DMA0CHST BIT_16 /* DMA channel 0 (RX0A/TX0A) Chaining Status */ #define DMA2CHST BIT_17 /* DMA channel 2 (RX1A/TX1A) Chaining Status */ #define DMA4CHST BIT_18 /* DMA channel 4 (RX2A/TX2A) Chaining Status */ #define DMA6CHST BIT_19 /* DMA channel 6 (RX3A/TX3A) Chaining Status */ #define DMA8CHST BIT_20 /* DMA channel 8 (LBUF0) Chaining Status */ #define DMA9CHST BIT_21 /* DMA channel 9 (LBUF1) Chaining Status */ #define DMA1CHST BIT_22 /* DMA channel 1 (RX0B/TX0B) Chaining Status */ #define DMA3CHST BIT_23 /* DMA channel 3 (RX1B/TX1B) Chaining Status */ #define DMA5CHST BIT_24 /* DMA channel 5 (RX2B/TX2B) Chaining Status */ #define DMA7CHST BIT_25 /* DMA channel 7 (RX3B/TX3B) Chaining Status */ #define DMA10CHST BIT_26 /* DMA channel 10 (EPB0) Chaining Status */ #define DMA11CHST BIT_27 /* DMA channel 11 (EPB1) Chaining Status */ #define DMA12CHST BIT_28 /* DMA channel 12 (EPB2) Chaining Status */ #define DMA13CHST BIT_29 /* DMA channel 13 (EPB3) Chaining Status */ /* SDCTL - SDRAM Control Register bit definitions */ #define SDCL1 BIT_0 /* SDCL[1:0] - CAS Latency field */ #define SDCL2 BIT_1 /* (delay between RD cmd and data at o/p pins) */ #define SDCL3 (BIT_0|BIT_1) /* configurable between 1 and 3 SDCLK cycles */ #define DSDCTL BIT_2 /* disable SDCLK0, /RAS, /CAS & SDCKE pins */ #define DSDCK1 BIT_3 /* disable SDCLK1 pin */ #define SDTRAS0 0x00000000 /* SDTRAS[3:0] - tRAS spec (active command delay)*/ #define SDTRAS1 BIT_4 /* (required delay between a Bank Activate */ #define SDTRAS2 BIT_5 /* command to a Precharge command) */ #define SDTRAS3 (BIT_4|BIT_5) /* configurable between 0 to 15 SDCLK cycles */ #define SDTRAS4 BIT_6 #define SDTRAS5 (BIT_4|BIT_6) #define SDTRAS6 (BIT_5|BIT_6) #define SDTRAS7 (BIT_4|BIT_5|BIT_6) #define SDTRAS8 BIT_7 #define SDTRAS9 (BIT_4|BIT_7) #define SDTRAS10 (BIT_5|BIT_7) #define SDTRAS11 (BIT_4|BIT_5|BIT_7) #define SDTRAS12 (BIT_6|BIT_7) #define SDTRAS13 (BIT_4|BIT_6|BIT_7) #define SDTRAS14 (BIT_5|BIT_6|BIT_7) #define SDTRAS15 (BIT_4|BIT_5|BIT_6|BIT_7) #define SDTRP0 0x00000000 /* SDTRP[2:0] - tRP spec (precharge delay) */ #define SDTRP1 BIT_8 /* (required delay between a precharge command */ #define SDTRP2 BIT_9 /* to a Bank Activate command) */ #define SDTRP3 (BIT_8|BIT_9) /* configurable between 1 to 7 cycles */ #define SDTRP4 BIT_10 #define SDTRP5 (BIT_8|BIT_10) #define SDTRP6 (BIT_9|BIT_10) #define SDTRP7 (BIT_8|BIT_9|BIT_10) #define SDPM BIT_11 /* SDRAM power-up mode bit */ #define SDPGS256 0x00000000 /* SDRAM Page Size - 256 words */ #define SDPGS512 BIT_12 /* SDRAM Page Size - 512 words */ #define SDPGS1024 BIT_13 /* SDRAM Page Size - 1024 words */ #define SDPGS2048 (BIT_12|BIT_13) /* SDRAM Page Size - 2048 words */ #define SDPSS BIT_14 /* SDRAM power-up sequence start command */ #define SDSRF BIT_15 /* Self refresh command */ #define SDEM0 BIT_16 /* Memory Bank 0 SDRAM Enable */ #define SDEM1 BIT_17 /* Memory Bank 1 SDRAM Enable */ #define SDEM2 BIT_18 /* Memory Bank 2 SDRAM Enable */ #define SDEM3 BIT_19 /* Memory Bank 3 SDRAM Enable */ #define SDBN2 0x00000000 /* SDRAM contains 2 memory banks */ #define SDBN4 BIT_20 /* SDRAM contains 4 memory banks */ #define SDCKRx1 BIT_21 /* 1:1 (full) SDCLK-to-CCLK (core-clock) ratio */ #define SDCKR_DIV2 0x00000000 /* 1:2 (one-half) SDCLK-to-CCLK ratio */ #define SDBUF BIT_23 /* Pipeline (reg. buf) option */ #define SDTRCD0 0x00000000 /* SDTRCD[2:0] - tRCD spec. (RAS-to-CAS delay) */ #define SDTRCD1 BIT_24 /* (required delay between a Bank Activate cmd */ #define SDTRCD2 BIT_25 /* and the start of the first RD or WR) */ #define SDTRCD3 (BIT_24|BIT_25) /* configurable between 1 to 7 SDCLK cycles */ #define SDTRCD4 BIT_26 #define SDTRCD5 (BIT_24|BIT_26) #define SDTRCD6 (BIT_25|BIT_26) #define SDTRCD7 (BIT_24|BIT_25|BIT_26) /* IOFLAG - programmable I/O status macro definitions */ #define FLG4 BIT_0 /* FLAG4 value (Low = '0', High = '1') */ #define FLG5 BIT_1 /* FLAG5 value (Low = '0', High = '1') */ #define FLG6 BIT_2 /* FLAG6 value (Low = '0', High = '1') */ #define FLG7 BIT_3 /* FLAG7 value (Low = '0', High = '1') */ #define FLG8 BIT_4 /* FLAG8 value (Low = '0', High = '1') */ #define FLG9 BIT_5 /* FLAG9 value (Low = '0', High = '1') */ #define FLG10 BIT_6 /* FLAG10 value (Low = '0', High = '1') */ #define FLG11 BIT_7 /* FLAG11 value (Low = '0', High = '1') */ /* IOFLAG - programmable I/O control macro definitions */ #define FLG4O BIT_8 /* FLAG4 control ('0' = flag input, '1' = flag output) */ #define FLG5O BIT_9 /* FLAG5 control ('0' = flag input, '1' = flag output) */ #define FLG6O BIT_10 /* FLAG6 control ('0' = flag input, '1' = flag output) */ #define FLG7O BIT_11 /* FLAG7 control ('0' = flag input, '1' = flag output) */ #define FLG8O BIT_12 /* FLAG8 control ('0' = flag input, '1' = flag output) */ #define FLG9O BIT_13 /* FLAG9 control ('0' = flag input, '1' = flag output) */ #define FLG10O BIT_14 /* FLAG10 control ('0' = flag input, '1' = flag output) */ #define FLG11O BIT_15 /* FLAG11 control ('0' = flag input, '1' = flag output) */ /*SPICTL register */ #define SPIEN BIT_0 /* SPI system enable */ #define SPRINT BIT_1 /* SPIRX buffer interrupt enable */ #define SPTINT BIT_2 /* SPITX buffer interrupt enable */ #define MS BIT_3 /* Master/Slave Mode bit */ #define CP BIT_4 /* SPICLK Polarity */ #define CPHASE BIT_5 /* SPICLK Phase */ #define DF BIT_6 /* Data Format */ #define WL8 0x00000000 /* SPI Word Length = 8 */ #define WL16 BIT_7 /* SPI Word Length = 16 */ #define WL32 (BIT_7|BIT_8) /* SPI Word Length = 32 */ #define BAUDR0 0x00000000 /* BAUDRATE = CCLK / 2**(2 + 0) = CCLK/4 */ #define BAUDR1 BIT_9 /* BAUDRATE = CCLK / 2**(2 + 1) = CCLK/8 */ #define BAUDR2 BIT_10 /* BAUDRATE = CCLK / 2**(2 + 2) = CCLK/16 */ #define BAUDR3 (BIT_9|BIT_10) /* BAUDRATE = CCLK / 2**(2 + 3) = CCLK/32 */ #define BAUDR4 BIT_11 /* BAUDRATE = CCLK / 2**(2 + 4) = CCLK/64 */ #define BAUDR5 (BIT_9|BIT_11) /* BAUDRATE = CCLK / 2**(2 + 5) = CCLK/128 */ #define BAUDR6 (BIT_10|BIT_11) /* BAUDRATE = CCLK / 2**(2 + 6) = CCLK/512 */ #define BAUDR7 (BIT_9|BIT_10|BIT_11) /* BAUDRATE = CCLK / 2**(2 + 7) = CCLK/1024 */ #define BAUDR8 BIT_12 /* BAUDRATE = CCLK / 2**(2 + 8) = CCLK/2048 */ #define BAUDR9 (BIT_9|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 9) = CCLK/4096 */ #define BAUDR10 (BIT_10|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 10) = CCLK/8192 */ #define BAUDR11 (BIT_9|BIT_10|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 11) = CCLK/16384 */ #define BAUDR12 (BIT_11|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 12) = CCLK/32768 */ #define BAUDR13 (BIT_9|BIT_11|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 13) = CCLK/65536 */ #define BAUDR14 (BIT_10|BIT_11|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 14) = CCLK/131072 */ #define BAUDR15 (BIT_9|BIT_10|BIT_11|BIT_12) /* BAUDRATE = CCLK / 2**(2 + 15) = CCLK/262144 */ #define TDMAEN BIT_13 /* SPITX transmit buffer DMA enable, DMA channel 9 */ #define PSSE BIT_14 /* Programmable slave device select */ #define FLS0 BIT_15 /* FLAG0 slave device select enable */ #define FLS1 BIT_16 /* FLAG1 slave device select enable */ #define FLS2 BIT_17 /* FLAG2 slave device select enable */ #define FLS3 BIT_18 /* FLAG3 slave device select enable */ #define NSMLS BIT_19 /* Seamless operation */ #define DCPH0 BIT_20 /* Select or deselect SPIDS~ between transfers */ #define DMISO BIT_25 /* Disable MISO Pin for Broadcast Mode */ #define OPD BIT_26 /* Open drain output enable for data pins */ #define RDMAEN BIT_27 /* SPIRX recevie buffer DMA enable, DMA channel 8 */ #define PACKEN BIT_28 /* 8-to-16 Bit Packing Enable */ #define SGN BIT_29 /* Sign-extend SPIRX/SPITX data */ #define SENDZ BIT_30 /* Send zero or repeat previous data when SPITX empty */ #define GM BIT_31 /* Retrieve or discard incoming data when SPIRX full */ /* SPISTAT register */ #define SPIF BIT_0 /* SPI transmit or receive transfer complete */ #define MME BIT_1 /* Multimaster error */ #define TXE BIT_2 /* SPITX transmission error (underflow) */ #define TXS0 BIT_3 /* TXS[0] - SPITX data buffer status */ #define TXS1 BIT_4 /* TXS[1] - SPITX data buffer status */ #define RBSY BIT_5 /* SPIRX reception error (overflow) */ #define RXS0 BIT_6 /* RXS[0] - SPIRX data buffer status */ #define RXS1 BIT_7 /* RXS[1] - SPIRX data buffer status */ /* LCTL register - 0xcc */ #define L0EN BIT_0 /* Link buffer 0 enable */ #define L0DEN BIT_1 /* Link buffer 0 DMA enable */ #define L0CHEN BIT_2 /* Link buffer 0 DMA chaining enable */ #define L0TRAN BIT_3 /* Link buffer 0 data direction */ #define L0EXT BIT_4 /* Link buffer 0 extended word size */ #define L0CLKD0 BIT_5 /* L0CLKD[0] Link buffer 0 CCLK divide ratio */ #define L0CLKD1 BIT_6 /* L0CLKD[1] Link buffer 0 CCLK divide ratio */ #define L0PDRDE BIT_8 /* Link Port 0 pulldown resister disable */ #define L0DPWID BIT_9 /* Link buffer 0 data path width */ #define L1EN BIT_10 /* Link buffer 1 enable */ #define L1DEN BIT_11 /* Link buffer 1 DMA enable */ #define L1CHEN BIT_12 /* Link buffer 1 DMA chaining enable */ #define L1TRAN BIT_13 /* Link buffer 1 data direction */ #define L1EXT BIT_14 /* Link buffer 1 extended word size */ #define L1CLKD0 BIT_15 /* L1CLKD[0] Link buffer 1 CCLK divide ratio */ #define L1CLKD1 BIT_16 /* L1CLKD[1] Link buffer 1 CCLK divide ratio */ #define L1PDRDE BIT_18 /* Link Port 1 pulldown resister disable */ #define L1DPWID BIT_19 /* Link buffer 1 data path width */ #define A0LB BIT_20 /* Link Port Assignment for LBUF0 - 2106x/21160 compatibility */ #define A1LB BIT_21 /* Link Port Assignment for LBUF1 - 2106x/21160 compatibility */ #define LAB0 BIT_20 /* Link Port Assignment for LBUF0 - new naming conventions */ #define LAB1 BIT_21 /* Link Port Assignment for LBUF1 - new naming conventions */ #define L0STAT0 BIT_22 /* L0STAT[0] - link buffer 0 status (read-only) */ #define L0STAT1 BIT_23 /* L0STAT[1] - link buffer 0 status (read-only) */ #define L1STAT0 BIT_24 /* L1STAT[0] - link buffer 1 status (read-only) */ #define L1STAT1 BIT_25 /* L1STAT[1] - link buffer 1 status (read-only) */ #define LRERR0 BIT_26 /* Link Buffer 0 receive pack error status */ #define LRERR1 BIT_27 /* Link Buffer 1 receive pack error status */ /* SP02MCTL & SP13MCTL registers */ #define MCE BIT_0 /* Multichannel Mode Enable */ #define MFD0 0x00000000 /* no frame delay, multichannel FS pulse in same SCLK cycle as first data bit */ #define MFD1 BIT_1 /* multichannel mode 1 cycle frame sync delay */ #define MFD2 BIT_2 /* multichannel mode 2 cycle frame sync delay */ #define MFD3 (BIT_1|BIT_2) /* multichannel mode 3 cycle frame sync delay */ #define MFD4 BIT_3 /* multichannel mode 4 cycle frame sync delay */ #define MFD5 (BIT_1|BIT_3) /* multichannel mode 5 cycle frame sync delay */ #define MFD6 (BIT_2|BIT_3) /* multichannel mode 6 cycle frame sync delay */ #define MFD7 (BIT_1|BIT_2|BIT_3) /* multichannel mode 7 cycle frame sync delay */ #define MFD8 BIT_4 /* multichannel mode 8 cycle frame sync delay */ #define MFD9 (BIT_1|BIT_4) /* multichannel mode 9 cycle frame sync delay */ #define MFD10 (BIT_2|BIT_4) /* multichannel mode 10 cycle frame sync delay */ #define MFD11 (BIT_1|BIT_2|BIT_4) /* multichannel mode 11 cycle frame sync delay */ #define MFD12 (BIT_3|BIT_4) /* multichannel mode 12 cycle frame sync delay */ #define MFD13 (BIT_1|BIT_3|BIT_4) /* multichannel mode 13 cycle frame sync delay */ #define MFD14 (BIT_2|BIT_3|BIT_4) /* multichannel mode 14 cycle frame sync delay */ #define MFD15 (BIT_1|BIT_2|BIT_3|BIT_4) /* multichannel mode 15 cycle frame sync delay */ #define NCH 0x00000FE0 /* Number of MCM channels - 1 */ #define NCH0 0x00000000 /* 1 Channel */ #define NCH1 BIT_5 /* 2 Channels */ #define NCH2 BIT_6 /* 3 Channels */ #define NCH3 (BIT_5|BIT_6) /* 4 Channels */ #define NCH4 BIT_7 /* 5 Channels */ #define NCH5 (BIT_5|BIT_7) /* 6 Channels */ #define NCH6 (BIT_6|BIT_7) /* 7 Channels */ #define NCH7 (BIT_5|BIT_6|BIT_7) /* 8 Channels */ #define NCH8 BIT_8 /* 9 Channels */ #define NCH9 (BIT_5|BIT_8) /* 10 Channels */ #define NCH10 (BIT_6|BIT_8) /* 11 Channels */ #define NCH11 (BIT_5|BIT_6|BIT_8) /* 12 Channels */ #define NCH12 (BIT_7|BIT_8) /* 13 Channels */ #define NCH13 (BIT_5|BIT_7|BIT_8) /* 14 Channels */ #define NCH14 (BIT_6|BIT_7|BIT_8) /* 15 Channels */ #define NCH15 (BIT_5|BIT_6|BIT_7|BIT_8) /* 16 Channels */ #define NCH16 BIT_9 /* 17 Channels */ #define NCH17 (BIT_5|BIT_9) /* 18 Channels */ #define NCH18 (BIT_6|BIT_9) /* 19 Channels */ #define NCH19 (BIT_5|BIT_6|BIT_9) /* 20 Channels */ #define NCH20 (BIT_7|BIT_9) /* 21 Channels */ #define NCH21 (BIT_5|BIT_7|BIT_9) /* 22 Channels */ #define NCH22 (BIT_6|BIT_7|BIT_9) /* 23 Channels */ #define NCH23 (BIT_5|BIT_6|BIT_7|BIT_9) /* 24 Channels */ #define NCH24 (BIT_8|BIT_9) /* 25 Channels */ #define NCH25 (BIT_5|BIT_8|BIT_9) /* 26 Channels */ #define NCH26 (BIT_6|BIT_8|BIT_9) /* 27 Channels */ #define NCH27 (BIT_5|BIT_6|BIT_8|BIT_9) /* 28 Channels */ #define NCH28 (BIT_7|BIT_8|BIT_9) /* 29 Channels */ #define NCH29 (BIT_5|BIT_7|BIT_8|BIT_9) /* 30 Channels */ #define NCH30 (BIT_6|BIT_7|BIT_8|BIT_9) /* 31 Channels */ #define NCH31 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_9) /* 32 Channels */ #define NCH32 BIT_10 /* 33 Channels */ #define NCH33 (BIT_5|BIT_10) /* 34 Channels */ #define NCH34 (BIT_6|BIT_10) /* 35 Channels */ #define NCH35 (BIT_5|BIT_6|BIT_10) /* 36 Channels */ #define NCH36 (BIT_7|BIT_10) /* 37 Channels */ #define NCH37 (BIT_5|BIT_7|BIT_10) /* 38 Channels */ #define NCH38 (BIT_6|BIT_7|BIT_10) /* 39 Channels */ #define NCH39 (BIT_5|BIT_6|BIT_7|BIT_10) /* 40 Channels */ #define NCH40 (BIT_8|BIT_10) /* 41 Channels */ #define NCH41 (BIT_5|BIT_8|BIT_10) /* 42 Channels */ #define NCH42 (BIT_6|BIT_8|BIT_10) /* 43 Channels */ #define NCH43 (BIT_5|BIT_6|BIT_8|BIT_10) /* 44 Channels */ #define NCH44 (BIT_7|BIT_8|BIT_10) /* 45 Channels */ #define NCH45 (BIT_5|BIT_7|BIT_8|BIT_10) /* 46 Channels */ #define NCH46 (BIT_6|BIT_7|BIT_8|BIT_10) /* 47 Channels */ #define NCH47 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_10) /* 48 Channels */ #define NCH48 (BIT_9|BIT_10) /* 49 Channels */ #define NCH49 (BIT_5|BIT_9|BIT_10) /* 50 Channels */ #define NCH50 (BIT_6|BIT_9|BIT_10) /* 51 Channels */ #define NCH51 (BIT_5|BIT_6|BIT_9|BIT_10) /* 52 Channels */ #define NCH52 (BIT_7|BIT_9|BIT_10) /* 53 Channels */ #define NCH53 (BIT_5|BIT_7|BIT_9|BIT_10) /* 54 Channels */ #define NCH54 (BIT_6|BIT_7|BIT_9|BIT_10) /* 55 Channels */ #define NCH55 (BIT_5|BIT_6|BIT_7|BIT_9|BIT_10) /* 56 Channels */ #define NCH56 (BIT_8|BIT_9|BIT_10) /* 57 Channels */ #define NCH57 (BIT_5|BIT_8|BIT_9|BIT_10) /* 58 Channels */ #define NCH58 (BIT_6|BIT_8|BIT_9|BIT_10) /* 59 Channels */ #define NCH59 (BIT_5|BIT_6|BIT_8|BIT_9|BIT_10) /* 60 Channels */ #define NCH60 (BIT_7|BIT_8|BIT_9|BIT_10) /* 61 Channels */ #define NCH61 (BIT_5|BIT_7|BIT_8|BIT_9|BIT_10) /* 62 Channels */ #define NCH62 (BIT_6|BIT_7|BIT_8|BIT_9|BIT_10) /* 63 Channels */ #define NCH63 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_9|BIT_10) /* 64 Channels */ #define NCH64 BIT_11 /* 65 Channels */ #define NCH65 (BIT_5|BIT_11) /* 66 Channels */ #define NCH66 (BIT_6|BIT_11) /* 67 Channels */ #define NCH67 (BIT_5|BIT_6|BIT_11) /* 68 Channels */ #define NCH68 (BIT_7|BIT_11) /* 69 Channels */ #define NCH69 (BIT_5|BIT_7|BIT_11) /* 70 Channels */ #define NCH70 (BIT_6|BIT_7|BIT_11) /* 71 Channels */ #define NCH71 (BIT_5|BIT_6|BIT_7|BIT_11) /* 72 Channels */ #define NCH72 (BIT_8|BIT_11) /* 73 Channels */ #define NCH73 (BIT_5|BIT_8|BIT_11) /* 74 Channels */ #define NCH74 (BIT_6|BIT_8|BIT_11) /* 75 Channels */ #define NCH75 (BIT_5|BIT_6|BIT_8|BIT_11) /* 76 Channels */ #define NCH76 (BIT_7|BIT_8|BIT_11) /* 77 Channels */ #define NCH77 (BIT_5|BIT_7|BIT_8|BIT_11) /* 78 Channels */ #define NCH78 (BIT_6|BIT_7|BIT_8|BIT_11) /* 79 Channels */ #define NCH79 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_11) /* 80 Channels */ #define NCH80 (BIT_9|BIT_11) /* 81 Channels */ #define NCH81 (BIT_5|BIT_9|BIT_11) /* 82 Channels */ #define NCH82 (BIT_6|BIT_9|BIT_11) /* 83 Channels */ #define NCH83 (BIT_5|BIT_6|BIT_9|BIT_11) /* 84 Channels */ #define NCH84 (BIT_7|BIT_9|BIT_11) /* 85 Channels */ #define NCH85 (BIT_5|BIT_7|BIT_9|BIT_11) /* 86 Channels */ #define NCH86 (BIT_6|BIT_7|BIT_9|BIT_11) /* 87 Channels */ #define NCH87 (BIT_5|BIT_6|BIT_7|BIT_9|BIT_11) /* 88 Channels */ #define NCH88 (BIT_8|BIT_9|BIT_11) /* 89 Channels */ #define NCH89 (BIT_5|BIT_8|BIT_9|BIT_11) /* 90 Channels */ #define NCH90 (BIT_6|BIT_8|BIT_9|BIT_11) /* 91 Channels */ #define NCH91 (BIT_5|BIT_6|BIT_8|BIT_9|BIT_11) /* 92 Channels */ #define NCH92 (BIT_7|BIT_8|BIT_9|BIT_11) /* 93 Channels */ #define NCH93 (BIT_5|BIT_7|BIT_8|BIT_9|BIT_11) /* 94 Channels */ #define NCH94 (BIT_6|BIT_7|BIT_8|BIT_9|BIT_11) /* 95 Channels */ #define NCH95 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_9|BIT_11) /* 96 Channels */ #define NCH96 (BIT_10|BIT_11) /* 97 Channel */ #define NCH97 (BIT_5|BIT_10|BIT_11) /* 98 Channels */ #define NCH98 (BIT_6|BIT_10|BIT_11) /* 99 Channels */ #define NCH99 (BIT_5|BIT_6|BIT_10|BIT_11) /* 100 Channels */ #define NCH100 (BIT_7|BIT_10|BIT_11) /* 101 Channels */ #define NCH101 (BIT_5|BIT_7|BIT_10|BIT_11) /* 102 Channels */ #define NCH102 (BIT_6|BIT_7|BIT_10|BIT_11) /* 103 Channels */ #define NCH103 (BIT_5|BIT_6|BIT_7|BIT_10|BIT_11) /* 104 Channels */ #define NCH104 (BIT_8|BIT_10|BIT_11) /* 105 Channels */ #define NCH105 (BIT_5|BIT_8|BIT_10|BIT_11) /* 106 Channels */ #define NCH106 (BIT_6|BIT_8|BIT_10|BIT_11) /* 107 Channels */ #define NCH107 (BIT_5|BIT_6|BIT_8|BIT_10|BIT_11) /* 108 Channels */ #define NCH108 (BIT_7|BIT_8|BIT_10|BIT_11) /* 109 Channels */ #define NCH109 (BIT_5|BIT_7|BIT_8|BIT_10|BIT_11) /* 110 Channels */ #define NCH110 (BIT_6|BIT_7|BIT_8|BIT_10|BIT_11) /* 111 Channels */ #define NCH111 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_10|BIT_11) /* 112 Channels */ #define NCH112 (BIT_9|BIT_10|BIT_11) /* 113 Channels */ #define NCH113 (BIT_5|BIT_9|BIT_10|BIT_11) /* 114 Channels */ #define NCH114 (BIT_6|BIT_9|BIT_10|BIT_11) /* 115 Channels */ #define NCH115 (BIT_5|BIT_6|BIT_9|BIT_10|BIT_11) /* 116 Channels */ #define NCH116 (BIT_7|BIT_9|BIT_10|BIT_11) /* 117 Channels */ #define NCH117 (BIT_5|BIT_7|BIT_9|BIT_10|BIT_11) /* 118 Channels */ #define NCH118 (BIT_6|BIT_7|BIT_9|BIT_10|BIT_11) /* 119 Channels */ #define NCH119 (BIT_5|BIT_6|BIT_7|BIT_9|BIT_10|BIT_11) /* 120 Channels */ #define NCH120 (BIT_8|BIT_9|BIT_10|BIT_11) /* 121 Channels */ #define NCH121 (BIT_5|BIT_8|BIT_9|BIT_10|BIT_11) /* 122 Channels */ #define NCH122 (BIT_6|BIT_8|BIT_9|BIT_10|BIT_11) /* 123 Channels */ #define NCH123 (BIT_5|BIT_6|BIT_8|BIT_9|BIT_10|BIT_11) /* 124 Channels */ #define NCH124 (BIT_7|BIT_8|BIT_9|BIT_10|BIT_11) /* 125 Channels */ #define NCH125 (BIT_5|BIT_7|BIT_8|BIT_9|BIT_10|BIT_11) /* 126 Channels */ #define NCH126 (BIT_6|BIT_7|BIT_8|BIT_9|BIT_10|BIT_11) /* 127 Channels */ #define NCH127 (BIT_5|BIT_6|BIT_7|BIT_8|BIT_9|BIT_10|BIT_11) /* 128 Channels */ #define SPL BIT_12 /* SPORT 0&2 or SPORT 1&3 Internal Loopback Mode */ #define CHNL 0x007F0000 /* Current Channel Status (read-only) */ #define CHNL0 0x00000000 /* 1 Channel */ #define CHNL1 BIT_16 /* 2 Channels */ #define CHNL2 BIT_17 /* 3 Channels */ #define CHNL3 (BIT_16|BIT_17) /* 4 Channels */ #define CHNL4 BIT_18 /* 5 Channels */ #define CHNL5 (BIT_16|BIT_18) /* 6 Channels */ #define CHNL6 (BIT_17|BIT_18) /* 7 Channels */ #define CHNL7 (BIT_16|BIT_17|BIT_18) /* 8 Channels */ #define CHNL8 BIT_19 /* 9 Channels */ #define CHNL9 (BIT_16|BIT_19) /* 10 Channels */ #define CHNL10 (BIT_17|BIT_19) /* 11 Channels */ #define CHNL11 (BIT_16|BIT_17|BIT_19) /* 12 Channels */ #define CHNL12 (BIT_18|BIT_19) /* 13 Channels */ #define CHNL13 (BIT_16|BIT_18|BIT_19) /* 14 Channels */ #define CHNL14 (BIT_17|BIT_18|BIT_19) /* 15 Channels */ #define CHNL15 (BIT_16|BIT_17|BIT_18|BIT_19) /* 16 Channels */ #define CHNL16 BIT_20 /* 17 Channels */ #define CHNL17 (BIT_16|BIT_20) /* 18 Channels */ #define CHNL18 (BIT_17|BIT_20) /* 19 Channels */ #define CHNL19 (BIT_16|BIT_17|BIT_20) /* 20 Channels */ #define CHNL20 (BIT_18|BIT_20) /* 21 Channels */ #define CHNL21 (BIT_16|BIT_18|BIT_20) /* 22 Channels */ #define CHNL22 (BIT_17|BIT_18|BIT_20) /* 23 Channels */ #define CHNL23 (BIT_16|BIT_17|BIT_18|BIT_20) /* 24 Channels */ #define CHNL24 (BIT_19|BIT_20) /* 25 Channels */ #define CHNL25 (BIT_16|BIT_19|BIT_20) /* 26 Channels */ #define CHNL26 (BIT_17|BIT_19|BIT_20) /* 27 Channels */ #define CHNL27 (BIT_16|BIT_17|BIT_19|BIT_20) /* 28 Channels */ #define CHNL28 (BIT_18|BIT_19|BIT_20) /* 29 Channels */ #define CHNL29 (BIT_16|BIT_18|BIT_19|BIT_20) /* 30 Channels */ #define CHNL30 (BIT_17|BIT_18|BIT_19|BIT_20) /* 31 Channels */ #define CHNL31 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_20) /* 32 Channels */ #define CHNL32 BIT_21 /* 33 Channels */ #define CHNL33 (BIT_16|BIT_21) /* 34 Channels */ #define CHNL34 (BIT_17|BIT_21) /* 35 Channels */ #define CHNL35 (BIT_16|BIT_17|BIT_21) /* 36 Channels */ #define CHNL36 (BIT_18|BIT_21) /* 37 Channels */ #define CHNL37 (BIT_16|BIT_18|BIT_21) /* 38 Channels */ #define CHNL38 (BIT_17|BIT_18|BIT_21) /* 39 Channels */ #define CHNL39 (BIT_16|BIT_17|BIT_18|BIT_21) /* 40 Channels */ #define CHNL40 (BIT_19|BIT_21) /* 41 Channels */ #define CHNL41 (BIT_16|BIT_19|BIT_21) /* 42 Channels */ #define CHNL42 (BIT_17|BIT_19|BIT_21) /* 43 Channels */ #define CHNL43 (BIT_16|BIT_17|BIT_19|BIT_21) /* 44 Channels */ #define CHNL44 (BIT_18|BIT_19|BIT_21) /* 45 Channels */ #define CHNL45 (BIT_16|BIT_18|BIT_19|BIT_21) /* 46 Channels */ #define CHNL46 (BIT_17|BIT_18|BIT_19|BIT_21) /* 47 Channels */ #define CHNL47 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_21) /* 48 Channels */ #define CHNL48 (BIT_20|BIT_21) /* 49 Channels */ #define CHNL49 (BIT_16|BIT_20|BIT_21) /* 50 Channels */ #define CHNL50 (BIT_17|BIT_20|BIT_21) /* 51 Channels */ #define CHNL51 (BIT_16|BIT_17|BIT_20|BIT_21) /* 52 Channels */ #define CHNL52 (BIT_18|BIT_20|BIT_21) /* 53 Channels */ #define CHNL53 (BIT_16|BIT_18|BIT_20|BIT_21) /* 54 Channels */ #define CHNL54 (BIT_17|BIT_18|BIT_20|BIT_21) /* 55 Channels */ #define CHNL55 (BIT_16|BIT_17|BIT_18|BIT_20|BIT_21) /* 56 Channels */ #define CHNL56 (BIT_19|BIT_20|BIT_21) /* 57 Channels */ #define CHNL57 (BIT_16|BIT_19|BIT_20|BIT_21) /* 58 Channels */ #define CHNL58 (BIT_17|BIT_19|BIT_20|BIT_21) /* 59 Channels */ #define CHNL59 (BIT_16|BIT_17|BIT_19|BIT_20|BIT_21) /* 60 Channels */ #define CHNL60 (BIT_18|BIT_19|BIT_20|BIT_21) /* 61 Channels */ #define CHNL61 (BIT_16|BIT_18|BIT_19|BIT_20|BIT_21) /* 62 Channels */ #define CHNL62 (BIT_17|BIT_18|BIT_19|BIT_20|BIT_21) /* 63 Channels */ #define CHNL63 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_20|BIT_21) /* 64 Channels */ #define CHNL64 BIT_22 /* 65 Channels */ #define CHNL65 (BIT_16|BIT_22) /* 66 Channels */ #define CHNL66 (BIT_17|BIT_22) /* 67 Channels */ #define CHNL67 (BIT_16|BIT_17|BIT_22) /* 68 Channels */ #define CHNL68 (BIT_18|BIT_22) /* 69 Channels */ #define CHNL69 (BIT_16|BIT_18|BIT_22) /* 70 Channels */ #define CHNL70 (BIT_17|BIT_18|BIT_22) /* 71 Channels */ #define CHNL71 (BIT_16|BIT_17|BIT_18|BIT_22) /* 72 Channels */ #define CHNL72 (BIT_19|BIT_22) /* 73 Channels */ #define CHNL73 (BIT_16|BIT_19|BIT_22) /* 74 Channels */ #define CHNL74 (BIT_17|BIT_19|BIT_22) /* 75 Channels */ #define CHNL75 (BIT_16|BIT_17|BIT_19|BIT_22) /* 76 Channels */ #define CHNL76 (BIT_18|BIT_19|BIT_22) /* 77 Channels */ #define CHNL77 (BIT_16|BIT_18|BIT_19|BIT_22) /* 78 Channels */ #define CHNL78 (BIT_17|BIT_18|BIT_19|BIT_22) /* 79 Channels */ #define CHNL79 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_22) /* 80 Channels */ #define CHNL80 (BIT_20|BIT_22) /* 81 Channels */ #define CHNL81 (BIT_16|BIT_20|BIT_22) /* 82 Channels */ #define CHNL82 (BIT_17|BIT_20|BIT_22) /* 83 Channels */ #define CHNL83 (BIT_16|BIT_17|BIT_20|BIT_22) /* 84 Channels */ #define CHNL84 (BIT_18|BIT_20|BIT_22) /* 85 Channels */ #define CHNL85 (BIT_16|BIT_18|BIT_20|BIT_22) /* 86 Channels */ #define CHNL86 (BIT_17|BIT_18|BIT_20|BIT_22) /* 87 Channels */ #define CHNL87 (BIT_16|BIT_17|BIT_18|BIT_20|BIT_22) /* 88 Channels */ #define CHNL88 (BIT_19|BIT_20|BIT_22) /* 89 Channels */ #define CHNL89 (BIT_16|BIT_19|BIT_20|BIT_22) /* 90 Channels */ #define CHNL90 (BIT_17|BIT_19|BIT_20|BIT_22) /* 91 Channels */ #define CHNL91 (BIT_16|BIT_17|BIT_19|BIT_20|BIT_22) /* 92 Channels */ #define CHNL92 (BIT_18|BIT_19|BIT_20|BIT_22) /* 93 Channels */ #define CHNL93 (BIT_16|BIT_18|BIT_19|BIT_20|BIT_22) /* 94 Channels */ #define CHNL94 (BIT_17|BIT_18|BIT_19|BIT_20|BIT_22) /* 95 Channels */ #define CHNL95 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_20|BIT_22) /* 96 Channels */ #define CHNL96 (BIT_21|BIT_22) /* 97 Channel */ #define CHNL97 (BIT_16|BIT_21|BIT_22) /* 98 Channels */ #define CHNL98 (BIT_17|BIT_21|BIT_22) /* 99 Channels */ #define CHNL99 (BIT_16|BIT_17|BIT_21|BIT_22) /* 100 Channels */ #define CHNL100 (BIT_18|BIT_21|BIT_22) /* 101 Channels */ #define CHNL101 (BIT_16|BIT_18|BIT_21|BIT_22) /* 102 Channels */ #define CHNL102 (BIT_17|BIT_18|BIT_21|BIT_22) /* 103 Channels */ #define CHNL103 (BIT_16|BIT_17|BIT_18|BIT_21|BIT_22) /* 104 Channels */ #define CHNL104 (BIT_19|BIT_21|BIT_22) /* 105 Channels */ #define CHNL105 (BIT_16|BIT_19|BIT_21|BIT_22) /* 106 Channels */ #define CHNL106 (BIT_17|BIT_19|BIT_21|BIT_22) /* 107 Channels */ #define CHNL107 (BIT_16|BIT_17|BIT_19|BIT_21|BIT_22) /* 108 Channels */ #define CHNL108 (BIT_18|BIT_19|BIT_21|BIT_22) /* 109 Channels */ #define CHNL109 (BIT_16|BIT_18|BIT_19|BIT_21|BIT_22) /* 110 Channels */ #define CHNL110 (BIT_17|BIT_18|BIT_19|BIT_21|BIT_22) /* 111 Channels */ #define CHNL111 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_21|BIT_22) /* 112 Channels */ #define CHNL112 (BIT_20|BIT_21|BIT_22) /* 113 Channels */ #define CHNL113 (BIT_16|BIT_20|BIT_21|BIT_22) /* 114 Channels */ #define CHNL114 (BIT_17|BIT_20|BIT_21|BIT_22) /* 115 Channels */ #define CHNL115 (BIT_16|BIT_17|BIT_20|BIT_21|BIT_22) /* 116 Channels */ #define CHNL116 (BIT_18|BIT_20|BIT_21|BIT_22) /* 117 Channels */ #define CHNL117 (BIT_16|BIT_18|BIT_20|BIT_21|BIT_22) /* 118 Channels */ #define CHNL118 (BIT_17|BIT_18|BIT_20|BIT_21|BIT_22) /* 119 Channels */ #define CHNL119 (BIT_16|BIT_17|BIT_18|BIT_20|BIT_21|BIT_22) /* 120 Channels */ #define CHNL120 (BIT_19|BIT_20|BIT_21|BIT_22) /* 121 Channels */ #define CHNL121 (BIT_16|BIT_19|BIT_20|BIT_21|BIT_22) /* 122 Channels */ #define CHNL122 (BIT_17|BIT_19|BIT_20|BIT_21|BIT_22) /* 123 Channels */ #define CHNL123 (BIT_16|BIT_17|BIT_19|BIT_20|BIT_21|BIT_22) /* 124 Channels */ #define CHNL124 (BIT_18|BIT_19|BIT_20|BIT_21|BIT_22) /* 125 Channels */ #define CHNL125 (BIT_16|BIT_18|BIT_19|BIT_20|BIT_21|BIT_22) /* 126 Channels */ #define CHNL126 (BIT_17|BIT_18|BIT_19|BIT_20|BIT_21|BIT_22) /* 127 Channels */ #define CHNL127 (BIT_16|BIT_17|BIT_18|BIT_19|BIT_20|BIT_21|BIT_22) /* 128 Channels */ /* SPCTL0, SPCTL1, SPCTL2 and SPCTL3 registers */ #define SPEN_A BIT_0 /* SPORT enable primary A channel */ #define DTYPE0 0x00000000 /* right justify, fill unused MSBs with 0s */ #define DTYPE1 BIT_1 /* right justify, sign-extend into unused MSBs */ #define DTYPE2 BIT_2 /* compand using mu law */ #define DTYPE3 (BIT_1|BIT_2) /* compand using a law */ #define SENDN BIT_3 /* MSB or LSB first */ #define SLEN3 BIT_5 /* serial length 3 */ #define SLEN4 (BIT_4|BIT_5) /* serial length 4 */ #define SLEN5 BIT_6 /* serial length 5 */ #define SLEN6 (BIT_4|BIT_6) /* serial length 6 */ #define SLEN7 (BIT_5|BIT_6) /* serial length 7 */ #define SLEN8 (BIT_4|BIT_5|BIT_6) /* serial length 8 */ #define SLEN9 BIT_7 /* serial length 9 */ #define SLEN10 (BIT_4|BIT_7) /* serial length 10 */ #define SLEN11 (BIT_5|BIT_7) /* serial length 11 */ #define SLEN12 (BIT_4|BIT_5|BIT_7) /* serial length 12 */ #define SLEN13 (BIT_6|BIT_7) /* serial length 13 */ #define SLEN14 (BIT_4|BIT_6|BIT_7) /* serial length 14 */ #define SLEN15 (BIT_5|BIT_6|BIT_7) /* serial length 15 */ #define SLEN16 (BIT_4|BIT_5|BIT_6|BIT_7) /* serial length 16 */ #define SLEN17 BIT_8 /* serial length 17 */ #define SLEN18 (BIT_4|BIT_8) /* serial length 18 */ #define SLEN19 (BIT_5|BIT_8) /* serial length 19 */ #define SLEN20 (BIT_4|BIT_5|BIT_8) /* serial length 20 */ #define SLEN21 (BIT_6|BIT_8) /* serial length 21 */ #define SLEN22 (BIT_4|BIT_6|BIT_8) /* serial length 22 */ #define SLEN23 (BIT_5|BIT_6|BIT_8) /* serial length 23 */ #define SLEN24 (BIT_4|BIT_5|BIT_6|BIT_8) /* serial length 24 */ #define SLEN25 (BIT_7|BIT_8) /* serial length 25 */ #define SLEN26 (BIT_4|BIT_7|BIT_8) /* serial length 26 */ #define SLEN27 (BIT_5|BIT_7|BIT_8) /* serial length 27 */ #define SLEN28 (BIT_4|BIT_5|BIT_7|BIT_8) /* serial length 28 */ #define SLEN29 (BIT_6|BIT_7|BIT_8) /* serial length 29 */ #define SLEN30 (BIT_4|BIT_6|BIT_7|BIT_8) /* serial length 30 */ #define SLEN31 (BIT_5|BIT_6|BIT_7|BIT_8) /* serial length 31 */ #define SLEN32 (BIT_4|BIT_5|BIT_6|BIT_7|BIT_8) /* serial length 32 */ #define PACK BIT_9 /* 16-to-32 data packing */ #define MSTR BIT_10 /* I2S Mode only... TX/RX is master or slave */ #define ICLK BIT_10 /* internally ('1') or externally ('0') generated transmit or recieve SCLKx */ #define OPMODE BIT_11 /* I2S mode enable ('1') or DSP Serial Mode/Multichannel mode ('0') */ #define CKRE BIT_12 /* Clock edge for data and frame sync sampling (rx) or driving (tx) */ #define FSR BIT_13 /* transmit or receive frame sync (FSx) required */ #define IFS BIT_14 /* internally generated transmit or receive frame sync (FSx) */ #define IRFS BIT_14 /* internally generated receive FS0 or FS1 in multichannel mode */ #define DITFS BIT_15 /* (I2S & DSP serial modes only) Data Independent 'tx' FSx when DDIR bit = 1 */ #define LFS BIT_16 /* Active Low transmit or receive frame sync (FSx) */ #define LRFS BIT_16 /* SPORT0 and SPORT1 active low TDM frame sync FS0/FS1 in MC mode */ #define LTDV BIT_16 /* (MC Mode only) SPORT2/SPORT3 tx data valid ena in TDM mode - TDV2/TDV3 alternate pin config */ #define LFIRST BIT_16 /* (I2S Mode Only) transmit left channel first ('1'), or right channel first ('0') */ #define LAFS BIT_17 /* (DSP Serial Mode only) Late (vs early) frame sync FSx */ #define SDEN_A BIT_18 /* SPORT TXnA/RXnA DMA enable primary A channel */ #define SCHEN_A BIT_19 /* SPORT TXnA/RXnA DMA chaining enable primary A channel */ #define SDEN_B BIT_20 /* SPORT TXnB/RXnB DMA enable primary B channel */ #define SCHEN_B BIT_21 /* SPORT TXnB/RXnB DMA chaining enable primary B channel */ #define FS_BOTH BIT_22 /* (DSP Serial & I2S modes only) Issue FSx only if data is in both TXnA & TXnB regs */ #define SPEN_B BIT_24 /* SPORTx secondary B channel enable */ #define DDIR BIT_25 /* SPORT data buffer data dirrection '1' = transmitter, '0' = receiver */ #define DERR_B BIT_26 /* SPORTx secondary B overflow/underflow error status in DSP serial & I2S modes (read-only) */ #define DXS0_B BIT_27 /* SPORTx secondary B data buffer status in DSP Serial & I2S modes (read-only)*/ #define DXS1_B BIT_28 /* SPORTx secondary B data buffer status in DSP Serial & I2S modes (read-only)*/ #define DERR_A BIT_29 /* SPORTx primary A overflow/underflow error status in DSP Serial & I2S modes (read-only) */ #define TUVF_A BIT_29 /* SPORT2 and SPORT3 TX2A/TX3A underflow status in MC mode (read-only, sticky)*/ #define ROVF_A BIT_29 /* SPORT0 and SPORT1 RX0A/RX1A overflow status in MC mode (read-only, sticky)*/ #define DXS0_A BIT_30 /* SPORTx primary A data buffer status in DSP serial and I2S modes (read-only)*/ #define DXS1_A BIT_31 /* SPORTx primary A data buffer status in DSP serial and I2S modes (read-only)*/ #define RXS0_A BIT_30 /* SPORT0 and SPORT1 RX0A/RX1A data buffer status in MC mode (read-only)*/ #define RXS1_A BIT_31 /* SPORT0 and SPORT1 RX0A/RX1A data buffer status in MC mode (read-only)*/ #define TXS0_A BIT_30 /* SPORT2 and SPORT3 TX2A/TX3A data buffer status in MC mode (read-only)*/ #define TXS1_A BIT_31 /* SPORT2 and SPORT3 TX2A/TX3A data buffer status in MC mode (read-only) */ #endif