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Department of Microelectronic Systems, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology

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Bitmap on VGA screen

Task: Design a module generating VGA signals of the following functionality:

the module should generate the following signals: 1-bit colours: R (red_o), G (grn_o), and B (blu_o), vertical synchronization (vs_o) and horizontal (hs_o);
signals must conform to VGA standard with 60Hz, 640x480 pixels;
colour of the background on VGA screen should be changeable with switches on the Spartan-3 board. Each switch should turn on a single colour: SW5_i - red, sw6_i - green and sw7_i - blue;
a rectangle of size 256 x 96 pixels should be placed in the centre of the screen;
bitmap in BMP format should be read from ROM and displayed in the above mentioned rectangle;
ROM has to be generated using Xilinx ISE8.1i Core Generator;
additional inputs to the module: clock 50MHz (clk_i) and asynchronous reset(rst_i).

Write a testbench. Before implementing the design, a simulation must be run using the testbench.

Additional information:

Fig. 1 Picture to display on VGA screen

Picture in format coe and bmp.

UCF file, Digilent Spartan-3, Spartan-3 3S200 FT256-4:
# Clock:
NET "clk_i" LOC = "T9" ; # 50 MHz clock
NET "clk_i" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 15 ns HIGH 50 %;
# Push-buttons:
NET "rst_i" LOC = "L14" ; # pressed high BTN3
# VGA port:
NET "blu_o" LOC = "R11" ;
NET "grn_o" LOC = "T12" ;
NET "red_o" LOC = "R12" ;
NET "hs_o" LOC = "R9" ; # horizontal sync
NET "vs_o" LOC = "T10" ; # vertical sync
# Slide switches
NET "sw5_i" LOC = "J13" ; # active high when in UP position
NET "sw6_i" LOC = "K14" ; # active high when in UP position
NET "sw7_i" LOC = "K13" ; # active high when in UP position