Examples of VHDL and Verilog® code
Sequential process with asynchronous reset:
VHDL: |
Verilog®: |
process (clk,rst)
begin
if rst='1' then
|
... place reset handling here... |
|
elsif clk'event and clk='1' then
|
... place operations on clock edge here... |
|
end if;
end process; |
always @(posedge clk or posedge rst)
if (rst)
begin
|
... place reset handling here... |
|
end
else
begin
|
... place operations on clock edge here... |
|
end |
Generating clock in testbench:
signal clk : std_logic := '0';
...
clk <= not clk after 10ns;
Generating non-standard signal in testbench:
signal we1 : std_logic;
...
we1 <= '0', '1' after 10ns, '0' after 25ns, '1' after 30ns;
Instantiation of components:
File: a.vhd:
----------- ENTITY A: ------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity a is
port (
a1 : in std_logic;
a2 : in std_logic;
a3 : out std_logic
);
end entity;
architecture beh of a is
begin
...
end architecture;
----------------------------------------------------
File: b.vhd:
----------- ENTITY B: ------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (
b1 : in std_logic;
b2 : in std_logic;
b3 : in std_logic;
b4 : out std_logic
);
end entity;
architecture beh of b is
signal tmp : std_logic;
component a is
port (
a1 : in std_logic;
a2 : in std_logic;
a3 : out std_logic
);
end component;
begin
X1: a port map (a1 => b1, a2 => b2, a3 => tmp);
X2: a port map (a1 => tmp, a2 => b3, a3 => b4);
end architecture;
----------------------------------------------------