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Department of Microelectronic Systems, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology

Polska wersja

HDL Languages

Rules for passing the course:

• Lecture (15 hrs/semester):
• 50 points = 2 tests: test I: 25 points, test II: 25 points  (major-related learning outcome [K_U16])
• attendance to the lecture: +5 pts.
• test = 40 questions
• calculation of points:
• points_for_test1 = (no_of_correct_answers1 - 10)*25/30
• points_for_test2 = (no_of_correct_answers2 - 10)*25/30
• Laboratory (30 hrs/semester):
• 50 points.  (major-related learning outcome [K_U16])
• Final deadline to complete exercises is on the last lab in the semester for each laboratory group.
• Condition necessary for passing the course:
• At least 25 points for tests (sum of test I + test II) and at least 25 points for lab.
• Grading system:
• ≥90 pts. ==> grade 5
• ≥80 pts. ==> grade 4,5
• ≥70 pts. ==> grade 4
• ≥60 pts. ==> grade 3,5
• ≥50 pts. ==> grade 3
• <50 pts. ==> grade 2
• Rules for assessing the student

Lecture

• Lecture materials (in Polish) (PDF)

Laboratory

• Laboratory exercises:

• No.	Exercise	Design entry	Approximate time	Points
  Exercise 1	Parity Generator	Verilog	2x45 min.	4
  Exercise 2	Frequency Divider	Verilog	2x45 min.	4
  Exercise 3	Port RS-232	Verilog	4x45 min.	8
  Exercise 4	Real Time Clock	VHDL	6x45 min.	10
  Exercise 5	Simple calculator with PS/2 keyboard	VHDL	8x45 min.	12
  Exercise 6	Testing and implementation of 128-bit AES encryption block	VHDL	remaining	12

Additional information:

• Spartan 3 - short FPGA design tutorial
• User Manual Digilent Spartan-3 board
• Reading PS/2 keyboard
• Wikipedia: RS-232