Quick Reference for FPGA Design (Vivado)

Vivado 2018

The manual describes the steps necessary to enter the HDL code and perform the simulation, and then the synthesis, implementation and programming of the FPGA system on the example of the Digilent Corporation Nexys A7 test board with the XC7A100T-1CSG324C chip (package: CSG324, speed grade: -1):

• Create a new project
• HDL entry
• Design simulation (functional)
• Constraints
• Synthesis and implementation
• Programming the FPGA