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Department of Microelectronic Systems, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology

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Lab exercises for 4th semester students:

ATTENTION: Files *.vhd from exercise from 1 to 9 must be sent to:
lab@ue.eti.pg.gda.pl in form "ex_XXX_name1_name2.vhd"

Exercises must be completed in the exact sequence from the table below.

Final deadline to complete exercises is on the last lab in the semester for each laboratory group.

During presentation of the results, students must prove that they are authors of the design. In any case of doubts, severe consequences will be enforced.

Exercise No.
Name
Design entry
Approximate time
Mark

Exercise 1 Parity Generator schematic diagram 60 min. 2.0

Exercise 2 Counter in Gray code schematic diagram 60 min. 2.0

Exercise 3 Parity generator VHDL 60 min. 2.0

Exercise 4 Counter in Gray code VHDL 60 min. 2.0

Exercise 5 Frequency divider VHDL 90 min. 2.0

Exercise 6 LED Display Driver VHDL 90 min. 3.0

Exercise 7 Simple stop-watch VHDL 2x90 min. 3.5

Exercise 8 PS/2 keyboard readout
VHDL 2x90 min. 4.0

Exercise 9 Port RS-232
VHDL 2x90 min. 4.5

Exercise 10 Bitmap on VGA screen
VHDL 2x90 min. 5.0

Exercise No.	Name	Design entry	Approximate time	Mark
Exercise 1	Parity Generator	schematic diagram	60 min.	2.0
Exercise 2	Counter in Gray code	schematic diagram	60 min.	2.0
Exercise 3	Parity generator	VHDL	60 min.	2.0
Exercise 4	Counter in Gray code	VHDL	60 min.	2.0
Exercise 5	Frequency divider	VHDL	90 min.	2.0
Exercise 6	LED Display Driver	VHDL	90 min.	3.0
Exercise 7	Simple stop-watch	VHDL	2x90 min.	3.5
Exercise 8	PS/2 keyboard readout	VHDL	2x90 min.	4.0
Exercise 9	Port RS-232	VHDL	2x90 min.	4.5
Exercise 10	Bitmap on VGA screen	VHDL	2x90 min.	5.0

Lab exercises for 4th semester students:

Additional information: