Programmable Circuits Engineering (4^th semester)

dr inż. Miron Kłosowski   EA309

miron.klosowski@pg.edu.pl

Lecture:

Lecture content (in Polish): iup.ppt
VHDL tutorial (in English): tutorial.ppt

List of test questions (in Polish): iup-kolo.html
(students who have obtained at least a grade of 4.0 from the laboratory are exempt from the test)

Some lecture screencasts (in Polish):

Wektory

Procesy kombinacyjne cz. 1

Procesy kombinacyjne cz. 2

Układy kombinacyjne - dokończenie

Procesy sekwencyjne

Układy sekwencyjne

Maszyny stanów

Stany zabronione

Funkcje i procedury

Laboratory:

Laboratory exercises should be completed in the order presented in the table below.

When submitting each exercise, students have to prove that they are the authors of the presented project and have prepared it on their own.

Laboratory – possible work at home (VHDL code creation, simulation and trial synthesis):

The exercises can be prepared at home in advance and an appropriate functional simulation (testbench) to check their operation can be performed (in exercise 10, the functional simulation is not obligatory).

Then you can use the remote laboratory access, described in the next chapter, to run the exercise on the FPGA board.

Below is screencast about Vivado design software, which should be downloaded from www.xilinx.com (version webpack 2018.3) and run on a home computer (also with Windows 10). The screencast also includes tips on how to create a testbench for laboratory exercises.

VIVADO demonstration

Demonstration VIVADO (in Polish)

Below is screencast about an example of modeling and simulation. An example of contact vibration modeling and connection of this model to the simulated system are presented. The results of simulations with contact vibrations and modifications introduced to the simulated system in order to solve the problem of contact vibrations are presented.

Demonstration - contact vibration (in Polish)

The contact vibration modeling module is available here:  bounce.vhd

(can be used to test designs for resistance for vibration of contacts).

Laboratory – remote work possible (running the exercise on a board with an FPGA chip; recording a video demonstrating the operation of the system, simulation results and design files):

Booking an appointment and logging in to the remote lab

Remote work with FPGAs

Principles of evaluating laboratory tasks carried out remotely

Attention! A stationary exercise pass is required – switching to a remote pass is possible only when the epidemic situation worsens.

Laboratory – realization of exercises in room EA308:

Selection of FPGA board to program

Short digital circuit design guide using FPGA

VIVADO demonstration – FPGA Basys3 board programming (in Polish)

General remarks for all exercises:

The exercises are realized and passed in the order given in the table below.

The clock frequency is 100 MHz.

The type of FPGA chip that must be selected in the Vivado project settings: xc7a100tcsg324-1

The following Vivado warning can be ignored in all exercises:

[Constraints 18-5210] No constraints selected for write.

Exercise number	Exercise title	Estimated realization time	Final grade
1	Parity generator	1 h	2,0
2	Combinational circuit	1 h	2,0
3	Gray code counter	2 h	2,0
4	Johnson code counter	2 h	2,0
5	Frequency divider	3 h	2,0
6	LED display controller	3 h	3,0
7	Simple stopwatch	3 h	3,5
8	Keyboard readout	4 h	4,0
9	RS-232 port implementation	4 h	4,5
10	Bitmap on VGA display	5 h	5,0

Additional information:

• PS/2 keyboard readout
• RS-232 interface description (in Polish)
• Wikipedia: RS-232
• VGA signal generation
• BMP file structure