PROGRAMMABLE SYSTEMS ENGINEERING   6th semester

Polska wersja

 

Miron K³osowski, Ph.D.   EA309

miron.klosowski@pg.edu.pl

 

 

The lecture (available only in Polish):

 

Part 1/2 (VHDL & PLDs)

Part 2/2 (SystemC)

 

 

The test:

 

List of questions for the test

Final results

 

 

The laboratory (EA337):

 

The exercises: 1, 2, 3, 4 must be done in the presented order. You are free to approach other exercises in the order that suits your needs (although the exercise 8b should be done after the exercise 7).

Deadline for completion of laboratory exercises: the last lab date provided for the group to which the student belongs.

For each presentation of the exercise, students must prove that they are the authors of the presented project and have prepared it by themselves. If there are any doubts, the consequences will be severe.

 

Exercise number

Exercise name

Approximate exercise duration

Max. number of points

1

Parity generator

2 h

6

2

Gray counter

2 h

6

3

LED display driver

3 h

6

4

RS-232 port monitor

3 h

8

5 *

(a) Core Generator (version 1)

3 h

8

(b) Core Generator (version 2)

6

Picoblaze processor †

3 h

8
(+4 for extended version)

7

Embedded Development Kit

3 h

10

8 *

(a) DTMF transmitter and receiver (under reconstruction)

3 h

8

(b) Linux operating system in EDK

9

SystemC environment

3 h

10

 

Σ=70

*  choose one exercise

 

Total number of points from labs and test

 

Mark

> 90

5.0

81 – 90

4.5

71 – 80

4.0

61 – 70

3.5

50 – 60

3.0

< 50

2.0

 

To pass you need at least 35 points from laboratory and at least 15 points from the test.

Completing both exercises: 8a and 8b or both exercises: 5a and 5b (that is, a total of 10 exercises) and gaining more than 80 points in total for all exercises makes students eligible for exemption from the test (with a final mark of 5.0).

 

FPGA design quick reference (software: Xilinx ISE 10.1, FPGA: Spartan 3):

This manual describes the steps required to enter the HDL code and perform the simulation and then synthesize, implement and program the FPGA on the Digilent Corporation Spartan3 Starter Kit board with XC3S200 chip:

1.      Create a new project
Modifications to the procedure:
- In the ‘Top-level source type’ box of the window ‘Create New Project’ select HDL.
- In the ‘Preferred Language’ box of the window ‘Device Properties’ select VHDL.
- In the ‘Speed’ box of the ‘Device Properties’ window, select ‘-4’ instead of ‘-5’.

2.      Enter the HDL code

3.      Perform the functional simulation

4.      Perform the implementation

5.      Configure the FPGA

 

 

Spartan-3 Starter Kit Board User Guide

 

Examples of VHDL and Verilog code

 

 

†  Picoblaze processor programming hint (mem2bit):

The mem2bit script has been installed on the system to modify the memory of the Picoblaze program code without having to re-synthesize the entire project. The script modifies the contents of the *.bit file that is loaded into the programmable circuit via iMPACT software.

Usage of the script:

 

    mem2bit  program_name  project_name

 

program_name  is a *.mem file (enter the name without the extension) generated by the assembler,

project_name  is a *.bit file (enter the name without the extension) generated by the ISE software.

 

After you run the script, select the Block RAM module containing the program to be modified (refer to the instance name).

The previous * .bit file will be saved with the ‘old_’ prefix.

 

 

 

Additional documentation files for prototype boards available in the lab:  http://www.ue.eti.pg.gda.pl/isplab/doc